公开(公告)号：US5826049A

公开(公告)日：1998-10-20

申请号：US916630

申请日：1992-07-22

申请人： Yasuhiro Ogata ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Taturu Toba ,  Teruo Tanaka

发明人： Yasuhiro Ogata ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Taturu Toba ,  Teruo Tanaka

IPC分类号： G06F15/173 ,  G06F15/80 ,  G06F15/163

CPC分类号： G06F15/17368

摘要： In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.

摘要翻译： 为了确定消息到接收端处理器组的传送路径，处理器包括路由位生成电路，并且交换交换机包括部分广播路径控制电路和路径控制信息改变电路。 为了定义接收端处理器组的范围，网络包括传送控制电路。 交叉开关包括与输出端口和边界寄存器组相关联的传输控制电路。 当在输出端口的下游方向上从输入端口传送部分广播消息时，确定属于与连接到特定输入端口的连接的部分广播范围是否连接到特定输出端口，由此 特定的部分广播消息从相同的输出端口传送。

公开(公告)号：US5754792A

公开(公告)日：1998-05-19

申请号：US34359

申请日：1993-03-19

申请人： Shinichi Shutoh ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Shigeo Takeuchi ,  Teruo Tanaka

发明人： Shinichi Shutoh ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Shigeo Takeuchi ,  Teruo Tanaka

IPC分类号： G06F11/14 ,  G06F15/173 ,  H04L12/56 ,  H04Q11/04 ,  G06F13/00

CPC分类号： G06F15/17375 ,  G06F11/1443 ,  H04L49/1576 ,  H04L49/256 ,  H04Q11/0478

摘要： A parallel processor system including a plurality of processors. When packets of same destination PE number are inputted from different ports, the destination PE number is added with ID numbers of leading ports of split crossbar switches to which the different input ports belong, respectively, by using respective addition circuits, to thereby determine a transfer destination output port for the packets. A plurality of the split crossbar switches having different numbers of input/output ports are realized by partitioning a crossbar switch. By means of an input port select circuit provided in association with each of the output ports, an output request for the packet from the input port belonging to the split crossbar switch to which the associated output port belongs is accepted, while output requests for the packets from the input ports belonging to the other split crossbar switches are inhibited from being accepted, whereby transfer of broadcast packets are inhibited between the split crossbar switches belonging to a physically same crossbar switch. Such situation can be evaded in which same broadcast packets arrive at one and the same processor a number of times.

摘要翻译： 一种并行处理器系统，包括多个处理器。 当从不同的端口输入相同的目的地PE号码的分组时，通过使用各自的加法电路，分别将目的地PE号码分别与不同的输入端口所属的分离的交叉开关的前导端口的ID号相加，从而确定传送 目标输出端口为数据包。 通过划分交叉开关来实现具有不同数量的输入/输出端口的多个分开的交叉开关。 通过与每个输出端口相关联地提供的输入端口选择电路，接收来自属于相关联的输出端口所属的分离交叉开关的输入端口的分组的输出请求，同时对分组的输出请求 从属于其他分割交叉开关的输入端口被禁止被接受，从而在属于物理上相同的交叉开关的分开的交叉开关之间禁止广播分组的传送。 可以避免这种情况，其中相同的广播分组多次到达同一个处理器。

公开(公告)号：US5377333A

公开(公告)日：1994-12-27

申请号：US945483

申请日：1992-09-15

申请人： Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shinichi Shutoh ,  Yasuhiro Ogata ,  Shigeo Takeuchi ,  Tatsuru Toba

发明人： Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shinichi Shutoh ,  Yasuhiro Ogata ,  Shigeo Takeuchi ,  Tatsuru Toba

IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17375

摘要： Crossbar switches having 2.sup.n +1 ports and computing clusters are arranged so that each crossbar switch is connected to 2.sup.n processors. Auxiliary processors that perform parallel processing administrative functions and input/output functions are arranged at the remainder ports of the crossbar switches. Exchangers are provided to connect each processor and its crossbar switches. Parallel processing may be executed by the 2.sup.n processors independently of processing by the auxiliary processors for speed. One mounting unit is formed of a crossbar switch of one dimension, the processor group connected to that crossbar switch, and all of the crossbar switches of a different dimension that are connected to one of the processors of the one processor group. The parallel processor system is mounted by just combining mounting units with no need for special LSIs or frames or the like on which to mount the crossbar switches and without the interfaces that connect the processor and the network becoming concentrated in one place.

摘要翻译： 具有2n + 1个端口和计算集群的交叉开关被布置成使得每个交叉开关连接到2n个处理器。 执行并行处理管理功能和输入/输出功能的辅助处理器被布置在交叉开关的其余端口处。 提供交换器来连接每个处理器及其交叉开关。 独立于辅助处理器对速度的处理，可以由2n个处理器执行并行处理。 一个安装单元由一维的交叉开关构成，处理器组连接到该交叉开关，以及连接到一个处理器组的一个处理器的不同维度的所有交叉开关。 并行处理器系统仅通过组合安装单元来安装，不需要特殊的LSI或框架等，在其上安装交叉开关，并且没有连接处理器和网络的接口变得集中在一个地方。

公开(公告)号：US5758053A

公开(公告)日：1998-05-26

申请号：US189683

申请日：1994-02-01

申请人： Shigeo Takeuchi ,  Yasuhiro Inagaki ,  Junji Nakagoshi ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Hiroaki Fujii ,  Yoshiko Yasuda ,  Kiyohiro Obara ,  Taturu Toba ,  Masahiro Yamada

发明人： Shigeo Takeuchi ,  Yasuhiro Inagaki ,  Junji Nakagoshi ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Hiroaki Fujii ,  Yoshiko Yasuda ,  Kiyohiro Obara ,  Taturu Toba ,  Masahiro Yamada

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  H04J6/00 ,  H04L12/00

CPC分类号： G06F11/1443 ,  G06F11/0724 ,  G06F11/0784 ,  G06F11/10

摘要： Parallel processors communicate with each other over a network by transmitting messages that include destination processor information. A message controller for each processor in the network receives the messages and checks for faults in the message, particularly in the destination processor number contained in a first word of the message. If a fault occurs in the destination processor number, then the faulty message is transmitted to an appropriate processor for handling the fault. In this way the network operation is not suspended because of the fault and the message is not left in the network as a result of the error occurring in the destination processor number. The processor to which the faulty message is directed is determined by a substitute destination processor number contained in the message or is predetermined and set in another way, such as by a service processor. To recover from the fault, the processor receiving the faulty message can request that the message be retransmitted or the error can be corrected using an ECC, for example. If the faulty message cannot be retransmitted, then the processor or the host processor can request that the job to which the faulty message pertains be canceled by all of the processors executing that job without affecting the simultaneous execution of other jobs by the same processors.

摘要翻译： 并行处理器通过发送包含目标处理器信息的消息通过网络彼此进行通信。 用于网络中的每个处理器的消息控制器接收消息并检查消息中的故障，特别是在消息的第一个字中包含的目标处理器号码中。 如果目标处理器号码发生故障，则故障消息被传送到适当的处理器处理故障。 以这种方式，网络操作由于故障而不被暂停，并且由于目标处理器号码中出现错误，网络中没有留下该消息。 错误消息所针对的处理器由包含在消息中的替代目的地处理器号码确定，或者以另一种方式例如由服务处理器预先设定。 为了从故障中恢复，例如，接收到故障消息的处理器可以请求重传该消息或者使用ECC来纠正该错误。 如果故障消息不能重发，则处理器或主机处理器可以请求执行该作业的所有处理器取消与故障消息相关的作业，而不会影响同一处理器同时执行其他作业。

公开(公告)号：US5617545A

公开(公告)日：1997-04-01

申请号：US73075

申请日：1993-06-09

申请人： Yasuhiro Ogata ,  Shigeo Takeuchi ,  Taturu Toba ,  Shinichi Shutoh ,  Naoki Hamanaka

发明人： Yasuhiro Ogata ,  Shigeo Takeuchi ,  Taturu Toba ,  Shinichi Shutoh ,  Naoki Hamanaka

IPC分类号： G06F9/48 ,  G06F13/18 ,  G06F13/36 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F15/17375 ,  G06F13/18 ,  G06F13/36

摘要： A parallel computer network wherein an arbitration circuit for performing arbitrating operation over a plurality of processing requests at the same time at high speed is provided in a crossbar network control circuit to thereby prevent the processing requests not selected from being kept awaited for a long time. The arbitration circuit includes a priority bit change circuit which has a plurality of adders for adding a preset value to the priority information of the each awaited processing request and also has a plurality of comparators for detecting the requests being awaited.

摘要翻译： 一种并行计算机网络，其中在横向网络控制电路中提供用于在多个处理请求中高速同时执行仲裁操作的仲裁电路，从而防止未被选择的处理请求被长时间等待。 仲裁电路包括优先级位改变电路，该电路具有多个加法器，用于将预置值添加到每个等待处理请求的优先级信息中，并且还具有用于检测正在等待的请求的多个比较器。