公开(公告)号：US5826049A

公开(公告)日：1998-10-20

申请号：US916630

申请日：1992-07-22

申请人： Yasuhiro Ogata ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Taturu Toba ,  Teruo Tanaka

发明人： Yasuhiro Ogata ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Shinichi Shutoh ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Taturu Toba ,  Teruo Tanaka

IPC分类号： G06F15/173 ,  G06F15/80 ,  G06F15/163

CPC分类号： G06F15/17368

摘要： In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.

摘要翻译： 为了确定消息到接收端处理器组的传送路径，处理器包括路由位生成电路，并且交换交换机包括部分广播路径控制电路和路径控制信息改变电路。 为了定义接收端处理器组的范围，网络包括传送控制电路。 交叉开关包括与输出端口和边界寄存器组相关联的传输控制电路。 当在输出端口的下游方向上从输入端口传送部分广播消息时，确定属于与连接到特定输入端口的连接的部分广播范围是否连接到特定输出端口，由此 特定的部分广播消息从相同的输出端口传送。

公开(公告)号：US5617545A

公开(公告)日：1997-04-01

申请号：US73075

申请日：1993-06-09

申请人： Yasuhiro Ogata ,  Shigeo Takeuchi ,  Taturu Toba ,  Shinichi Shutoh ,  Naoki Hamanaka

发明人： Yasuhiro Ogata ,  Shigeo Takeuchi ,  Taturu Toba ,  Shinichi Shutoh ,  Naoki Hamanaka

IPC分类号： G06F9/48 ,  G06F13/18 ,  G06F13/36 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F15/17375 ,  G06F13/18 ,  G06F13/36

摘要： A parallel computer network wherein an arbitration circuit for performing arbitrating operation over a plurality of processing requests at the same time at high speed is provided in a crossbar network control circuit to thereby prevent the processing requests not selected from being kept awaited for a long time. The arbitration circuit includes a priority bit change circuit which has a plurality of adders for adding a preset value to the priority information of the each awaited processing request and also has a plurality of comparators for detecting the requests being awaited.

摘要翻译： 一种并行计算机网络，其中在横向网络控制电路中提供用于在多个处理请求中高速同时执行仲裁操作的仲裁电路，从而防止未被选择的处理请求被长时间等待。 仲裁电路包括优先级位改变电路，该电路具有多个加法器，用于将预置值添加到每个等待处理请求的优先级信息中，并且还具有用于检测正在等待的请求的多个比较器。

公开(公告)号：US5742766A

公开(公告)日：1998-04-21

申请号：US34805

申请日：1993-03-19

申请人： Shigeo Takeuchi ,  Hideo Wada ,  Naoki Hamanaka ,  Junji Nakagoshi ,  Teruo Tanaka ,  Yasuhiro Ogata ,  Taturu Toba ,  Mitsuyoshi Igai

发明人： Shigeo Takeuchi ,  Hideo Wada ,  Naoki Hamanaka ,  Junji Nakagoshi ,  Teruo Tanaka ,  Yasuhiro Ogata ,  Taturu Toba ,  Mitsuyoshi Igai

IPC分类号： G06F9/52 ,  G06F15/173 ,  G06F15/80 ,  G06F13/12

CPC分类号： G06F15/17343 ,  G06F15/17381

摘要： An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.

摘要翻译： 来自每个处理器的操作完成信号和收敛结果信号被传送到X方向互连开关，并且这些信号的AND在每个互连开关中以开关单元获得，该信号被发送到所有Y方向互连开关，通过 每个继电器开关中的同步信号继电器开关等，在互连开关中的每个开关单元中获得这些信号的AND，并且其结果通过每个同步信号继电器开关传送到每个处理器。 由此，来自所有处理器的操作完成信号和收敛结果信号的逻辑积的逻辑积并行发送到所有处理器。

公开(公告)号：US5386566A

公开(公告)日：1995-01-31

申请号：US853427

申请日：1992-03-18

申请人： Naoki Hamanaka ,  Junji Nakagoshi ,  Tatsuo Higuchi ,  Hiroyuki Chiba ,  Shin'ichi Shutoh ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

发明人： Naoki Hamanaka ,  Junji Nakagoshi ,  Tatsuo Higuchi ,  Hiroyuki Chiba ,  Shin'ichi Shutoh ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

IPC分类号： G06F9/46 ,  H04L29/00 ,  G06F13/00

CPC分类号： G06F9/544 ,  H04L29/00

摘要： In a parallel computer, in order to reduce the overhead of data transmissions between the processes, a data transmission from the virtual space of a process in a certain cluster to the virtual space of a process in other cluster is executed without copying the data to the buffer provided within the operating system. The real communication area resident in the real memory is provided in a part of the virtual space of the process, and an identifier unique within the cluster is given to the communication area. When the transmission process has issued a transmission instruction at the time of data transmission, the cluster address of the cluster in which the transmission destination process exists and the identifier of the communication area are determined based on the name of the transmission destination process. Then, the data is directly transmitted between the mutual real communication areas of the transmission originating process and the transmission destination process. Overhead for the data transmission between the processes can be reduced by avoiding making a copy of the data between the user space and the buffer provided within the operating system at the time of data transmission between the processes.

摘要翻译： 在并行计算机中，为了减少进程之间的数据传输的开销，执行从某个群集中的进程的虚拟空间到其他群集中的进程的虚拟空间的数据传输，而不将数据复制到 在操作系统中提供缓冲区。 驻留在真实存储器中的实际通信区域被提供在该进程的虚拟空间的一部分中，并且在群集内唯一的标识符被提供给通信区域。 当发送处理在数据发送时发出发送指示时，基于发送目的地处理的名称确定发送目的地处理所在的群集的群集地址和通信区域的标识符。 然后，数据在发送始发处理的相互实际通信区域和发送目的地处理之间直接发送。 可以通过在进程之间的数据传输时避免在用户空间和在操作系统内提供的缓冲区之间的数据的副本来复制用于进程之间的数据传输的开销。

公开(公告)号：US5825773A

公开(公告)日：1998-10-20

申请号：US853242

申请日：1992-03-18

申请人： Shin'ichi Shutoh ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

发明人： Shin'ichi Shutoh ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

IPC分类号： G06F15/173 ,  H04L12/18 ,  H04L12/931 ,  G06F13/00

CPC分类号： G06F15/17393 ,  H04L49/201 ,  H04L49/205

摘要： In a method of transferring packets in a network for a parallel processor system handling a one-to-one transfer packet to be transferred from a processor to another processor and a broadcast packet to be transferred from a processor to a plurality of other processors, a transfer request of a broadcast packet is preferentially selected and a check is made to detect whether or not a plurality of processors specified as receivers are in a state in which the packet can be received. The broadcast packet is transferred to the processors found to be in the state in which the packet can be received. The packet transfer is delayed for the other processors in a state in which the packet cannot be received. Namely, only when the state of the processors is changed to the state in which the packet can be received, the broadcast packet is transferred thereto.

摘要翻译： 在用于处理要从处理器传送到另一处理器的一对一传送分组的并行处理器系统的网络中传送分组的方法以及要从处理器传送到多个其他处理器的广播分组的方法中， 优先选择广播分组的传送请求，并进行检查，以检测指定为接收者的多个处理器是否处于可以接收分组的状态。 广播分组被传送到发现处于可以接收分组的状态的处理器。 在其中不能接收分组的状态下，其他处理器的分组传送被延迟。 也就是说，只有当处理器的状态改变为可以接收分组的状态时，广播分组被传送到其中。

公开(公告)号：US5377333A

公开(公告)日：1994-12-27

申请号：US945483

申请日：1992-09-15

申请人： Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shinichi Shutoh ,  Yasuhiro Ogata ,  Shigeo Takeuchi ,  Tatsuru Toba

发明人： Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shinichi Shutoh ,  Yasuhiro Ogata ,  Shigeo Takeuchi ,  Tatsuru Toba

IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17375

摘要： Crossbar switches having 2.sup.n +1 ports and computing clusters are arranged so that each crossbar switch is connected to 2.sup.n processors. Auxiliary processors that perform parallel processing administrative functions and input/output functions are arranged at the remainder ports of the crossbar switches. Exchangers are provided to connect each processor and its crossbar switches. Parallel processing may be executed by the 2.sup.n processors independently of processing by the auxiliary processors for speed. One mounting unit is formed of a crossbar switch of one dimension, the processor group connected to that crossbar switch, and all of the crossbar switches of a different dimension that are connected to one of the processors of the one processor group. The parallel processor system is mounted by just combining mounting units with no need for special LSIs or frames or the like on which to mount the crossbar switches and without the interfaces that connect the processor and the network becoming concentrated in one place.

摘要翻译： 具有2n + 1个端口和计算集群的交叉开关被布置成使得每个交叉开关连接到2n个处理器。 执行并行处理管理功能和输入/输出功能的辅助处理器被布置在交叉开关的其余端口处。 提供交换器来连接每个处理器及其交叉开关。 独立于辅助处理器对速度的处理，可以由2n个处理器执行并行处理。 一个安装单元由一维的交叉开关构成，处理器组连接到该交叉开关，以及连接到一个处理器组的一个处理器的不同维度的所有交叉开关。 并行处理器系统仅通过组合安装单元来安装，不需要特殊的LSI或框架等，在其上安装交叉开关，并且没有连接处理器和网络的接口变得集中在一个地方。

公开(公告)号：US5754792A

公开(公告)日：1998-05-19

申请号：US34359

申请日：1993-03-19

申请人： Shinichi Shutoh ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Shigeo Takeuchi ,  Teruo Tanaka

发明人： Shinichi Shutoh ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Shigeo Takeuchi ,  Teruo Tanaka

IPC分类号： G06F11/14 ,  G06F15/173 ,  H04L12/56 ,  H04Q11/04 ,  G06F13/00

CPC分类号： G06F15/17375 ,  G06F11/1443 ,  H04L49/1576 ,  H04L49/256 ,  H04Q11/0478

摘要： A parallel processor system including a plurality of processors. When packets of same destination PE number are inputted from different ports, the destination PE number is added with ID numbers of leading ports of split crossbar switches to which the different input ports belong, respectively, by using respective addition circuits, to thereby determine a transfer destination output port for the packets. A plurality of the split crossbar switches having different numbers of input/output ports are realized by partitioning a crossbar switch. By means of an input port select circuit provided in association with each of the output ports, an output request for the packet from the input port belonging to the split crossbar switch to which the associated output port belongs is accepted, while output requests for the packets from the input ports belonging to the other split crossbar switches are inhibited from being accepted, whereby transfer of broadcast packets are inhibited between the split crossbar switches belonging to a physically same crossbar switch. Such situation can be evaded in which same broadcast packets arrive at one and the same processor a number of times.

摘要翻译： 一种并行处理器系统，包括多个处理器。 当从不同的端口输入相同的目的地PE号码的分组时，通过使用各自的加法电路，分别将目的地PE号码分别与不同的输入端口所属的分离的交叉开关的前导端口的ID号相加，从而确定传送 目标输出端口为数据包。 通过划分交叉开关来实现具有不同数量的输入/输出端口的多个分开的交叉开关。 通过与每个输出端口相关联地提供的输入端口选择电路，接收来自属于相关联的输出端口所属的分离交叉开关的输入端口的分组的输出请求，同时对分组的输出请求 从属于其他分割交叉开关的输入端口被禁止被接受，从而在属于物理上相同的交叉开关的分开的交叉开关之间禁止广播分组的传送。 可以避免这种情况，其中相同的广播分组多次到达同一个处理器。

公开(公告)号：US20060288348A1

公开(公告)日：2006-12-21

申请号：US11485273

申请日：2006-07-13

申请人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Naoki Hamanaka

发明人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Naoki Hamanaka

IPC分类号： G06F9/46

CPC分类号： G06F9/5077 ,  G06F9/5083

摘要： Disclosed are a virtual computer system and method, wherein computer resources are automatically and optimally allocated to logical partitions according to loads to be accomplished by operating systems in the logical partitions and setting information based on a knowledge of workloads that run on the operating systems. Load measuring modules are installed on the operating systems in order to measure the loads to be accomplished by the operating systems. A manager designates the knowledge concerning the workloads on the operating systems through a user interface. An adaptive control module determines the allocation rations of the computer resources relative to the logical partitions according to the loads and the settings, and issues an allocation varying instruction to a hypervisor so as to thus instruct variation of allocations.

公开(公告)号：US06757788B2

公开(公告)日：2004-06-29

申请号：US09941834

申请日：2001-08-30

申请人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Hiromitsu Maeda ,  Naoki Hamanaka

发明人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Hiromitsu Maeda ,  Naoki Hamanaka

IPC分类号： G06F1300

CPC分类号： G06F12/0817 ,  G06F12/0815

摘要： A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an extended node larger than a block size of the internal cache of a CPU. When a memory access is performed, the access right memory is referred to, and if the node has an access right to the extended block including a target block, the block is accessed without cache coherence control at other nodes.

摘要翻译： 一种用于具有由网络互连的多个CPU节点，存储器节点和I / O节点的多CPU系统的高速缓存一致性控制系统。 每个CPU节点控制电路具有访问权限存储器，用于以比CPU的内部高速缓存的块大小更大的扩展节点来管理节点的访问权限。 当执行存储器访问时，参考访问权限存储器，并且如果节点对包括目标块的扩展块具有访问权限，则在其他节点处访问该块而不进行高速缓存一致性控制。

公开(公告)号：US06728258B1

公开(公告)日：2004-04-27

申请号：US09456383

申请日：1999-12-08

申请人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

发明人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

IPC分类号： H04L1266

CPC分类号： G06F15/17375 ,  G06F12/0833 ,  G06F2212/1016 ,  G06F2212/206

摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

摘要翻译： 在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路 请求以下列方式。 对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。 对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。 对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。