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17 条记录 (耗时 0.02 秒)

    Current detection circuit of bidirectional switch
    2.
    发明申请
    Current detection circuit of bidirectional switch 有权
    双向开关电流检测电路

    公开(公告)号：US20050189981A1

    公开(公告)日：2005-09-01

    申请号：US10998799

    申请日：2004-11-30

    申请人： Shinichiro Matsunaga

    发明人： Shinichiro Matsunaga

    IPC分类号： G01R19/165 ,  G01R27/08 ,  H02J7/00 ,  H03D1/00

    CPC分类号： G01R19/16571 ,  G01R19/16542

    摘要： A bidirectional main switch includes two main switches M1 and M2 formed of two main MOSFET's Q1 and Q2, respectively; a bidirectional mirror switch including two mirror switches M3 and M4 formed of two mirror MOSFET's Q3 and Q4, respectively, both being formed so as to allow a small current (a mirror current) to flow therein in a specified ratio to a current in the main MOSFET's Q1 and Q2; and an operational amplifier Op1 forming a feed back amplifying circuit having power supplied from two power sources of a positive source VDD and a negative source—VDD, being connected between the end of the bidirectional main switch and the end of the bidirectional mirror switch, and allowing the mirror current to flow in the bidirectional mirror switch through a sensing resistor Rs so as to equalize voltages at the ends of the two bidirectional switches, with which the mirror current, consequently a battery charge and discharge current, is detected from a voltage across the sensing resistor. Thus, a bidirectional current flowing the bidirectional main switch for cutting off an excessive charge current and an excessive discharge current of a battery E can be detected by a simple circuit with low power losses and a high accuracy.

    摘要翻译： 双向主开关包括分别由两个主MOSFET的Q 1和Q 2形成的两个主开关M 1和M 2; 分别包括由两个反射镜MOSFET的Q 3和Q 4形成的两个反射镜开关M 3和M 4的双向反射镜开关，两个反射镜开关M 3和M 4都形成为允许小电流（反射镜电流）以特定的比例流向其中 主MOSFET的Q1和Q2中的电流; 以及形成反馈放大电路的运算放大器Op1，其连接在双向主开关的端部和双向反射镜开关的端部之间，具有从正源VDD和负电源VDD的两个电源供给的电力， 并且允许反射镜电流在双向反射镜开关中通过感测电阻器Rs流动，以便均衡两个双向开关的端部处的电压，从而从其电压检测反射镜电流，从而检测电池充电和放电电流 跨越感测电阻。 因此，可以通过具有低功率损耗和高精度的简单电路来检测流过双向主开关的双向电流，以切断电池E的过充电电流和过大的放电电流。

    Semiconductor device and semiconductor device manufacturing method
    3.
    发明申请
    Semiconductor device and semiconductor device manufacturing method 审中-公开
    半导体器件和半导体器件制造方法

    公开(公告)号：US20090085106A1

    公开(公告)日：2009-04-02

    申请号：US12232989

    申请日：2008-09-26

    申请人： Shinichiro Matsunaga

    发明人： Shinichiro Matsunaga

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/41766 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/7835

    摘要： A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed.

    摘要翻译： 提供了相对于基板的表面积具有低导通电阻和高集成度的半导体器件。 在半导体器件中，在设置在半导体衬底上的元件形成区域中设置第一沟槽，第二沟槽和第三沟槽。 金属沉积在第一沟槽和第二沟槽内，分别形成漏电极和源电极。 多晶硅沉积在第三沟槽内部，栅极绝缘膜介于其间，形成栅电极。

    Indole derivatives as somatostatin agonists or antagonists
    4.
    发明申请
    Indole derivatives as somatostatin agonists or antagonists 审中-公开
    吲哚衍生物作为生长抑素激动剂或拮抗剂

    公开(公告)号：US20060223826A1

    公开(公告)日：2006-10-05

    申请号：US10534725

    申请日：2003-11-18

    申请人： Hidenori Abe ,  Shinichiro Matsunaga ,  Shiro Takekawa ,  Masanori Watanabe

    发明人： Hidenori Abe ,  Shinichiro Matsunaga ,  Shiro Takekawa ,  Masanori Watanabe

    IPC分类号： A61K31/496 ,  A61K31/454 ,  C07D403/02

    CPC分类号： C07D401/12 ,  C07D209/20 ,  C07D209/42 ,  C07D401/14 ,  C07D403/12 ,  C07D405/12 ,  C07D405/14 ,  C07D417/12 ,  C07D417/14 ,  C07D495/04

    摘要： The present invention provide a compound of the formula (I) wherein ring A represents an aromatic ring optionally having substituents; B, Y and Ya are the same or different and each represents a bond, etc.; R1 and R2 are the same or different and each represents a hydrogen atom, etc.; R3 represents a hydrogen atom, etc.; R4 and R5 are the same or different and each represents a hydrogen, etc.; R6 represents an indolyl group optionally having substituents; and Z and Za are the same or different and each represents a hydrogen atom, etc.; or a salt thereof or a prodrug thereof, having a somatostatin receptor binding inhibition activity and is useful for preventing and/or treating diseases associated with somatostatin.

    摘要翻译： 本发明提供式（I）的化合物，其中环A表示任选具有取代基的芳环; B，Y和Ya是相同或不同的，每个代表一个债券等; R 1和R 2相同或不同，各自表示氢原子等; R 3表示氢原子等; R 4和R 5相同或不同，各自表示氢等; R 6表示任选具有取代基的吲哚基; Z和Za相同或不同，各自表示氢原子等; 或其盐或其前药，具有生长抑素受体结合抑制活性，并且可用于预防和/或治疗与生长抑素相关的疾病。

    Semiconductor device with low on resistance
    5.
    发明授权
    Semiconductor device with low on resistance 有权
    具有低导通电阻的半导体器件

    公开(公告)号：US08921928B2

    公开(公告)日：2014-12-30

    申请号：US13099119

    申请日：2011-05-02

    申请人： Shinichiro Matsunaga

    发明人： Shinichiro Matsunaga

    IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L29/45

    CPC分类号： H01L29/41766 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/7835

    摘要： A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed.

    摘要翻译： 提供了相对于基板的表面积具有低导通电阻和高集成度的半导体器件。 在半导体器件中，在设置在半导体衬底上的元件形成区域中设置第一沟槽，第二沟槽和第三沟槽。 金属沉积在第一沟槽和第二沟槽内，分别形成漏电极和源电极。 多晶硅沉积在第三沟槽内部，栅极绝缘膜介于其间，形成栅电极。

    Semiconductor device, battery protection circuit and battery pack
    6.
    发明授权
    Semiconductor device, battery protection circuit and battery pack 失效
    半导体器件，电池保护电路和电池组

    公开(公告)号：US08378418B2

    公开(公告)日：2013-02-19

    申请号：US12805965

    申请日：2010-08-26

    申请人： Mutsumi Kitamura ,  Akio Sugi ,  Naoto Fujishima ,  Shinichiro Matsunaga

    发明人： Mutsumi Kitamura ,  Akio Sugi ,  Naoto Fujishima ,  Shinichiro Matsunaga

    IPC分类号： H01L29/66

    CPC分类号： H01M10/4207 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/781 ,  H01L29/7827 ,  H01M10/48

    摘要： A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.

    摘要翻译： 双向沟槽横向功率MOSFET（TLPM）可实现高击穿电压和低导通电阻。 在两端具有圆形部分的多个直形岛被沟槽布置包围。 这些岛提供第一n个源区，并且在岛的外部形成第二n源区。 利用这种图案，在第二n个源极区域处于高电位的情况下，在第一n个源极区域处于高电位的情况下的击穿电压可以高于击穿电压。 或者，在不改变击穿电压的情况下，可以降低导通电阻。

    Battery protective device and semiconductor integrated circuit device
    10.
    发明授权
    Battery protective device and semiconductor integrated circuit device 失效
    电池保护装置和半导体集成电路装置

    公开(公告)号：US07737664B2

    公开(公告)日：2010-06-15

    申请号：US12149767

    申请日：2008-05-07

    申请人： Shinichiro Matsunaga

    发明人： Shinichiro Matsunaga

    IPC分类号： H02J7/00

    CPC分类号： H03K17/6874 ,  H01M10/0525 ,  H01M10/44 ,  H01M10/48 ,  H02J7/0031 ,  H02J2007/0037 ,  H02J2007/004 ,  H03K17/063 ,  H03K17/0822

    摘要： A battery protective device that protects against battery damage and semiconductor destruction from overdischarge and overcharge of the battery. Resistance across switching elements is controllable to prevent current leakage through parasitic dipole elements in the integrated circuit. Current is detected with an overdischarge detecting circuit and an overcharge detecting circuit. Direction of the current to/from the battery is detected by discharge overcurrent and charge overcurrent detecting circuits. Switching discharge FETs and charge FETs are enabled as independently controlled, ON-OFF parallel switching elements, interposed in series in the charge/discharge current path of the battery. Only a part of the discharge or charge switching FETs can be turned ON and OFF for accurate current control in accordance with the detected current and its direction.

    摘要翻译： 一种电池保护装置，可防止电池的过度放电和过充电造成电池损坏和半导体破坏。 开关元件之间的电阻是可控的，以防止集成电路中寄生偶极子元件的电流泄漏。 用过放电检测电路和过充电检测电路检测电流。 通过放电过电流和电荷过电流检测电路检测到电池电流的方向。 开关放电FET和充电FET作为独立控制的ON-OFF并联开关元件被串联插入电池的充电/放电电流路径中。 根据检测到的电流及其方向，只有一部分放电或充电开关FET可以被导通和截止以进行精确的电流控制。