Microcomputer system
    1.
    发明申请
    Microcomputer system 有权
    微电脑系统

    公开(公告)号:US20090106572A1

    公开(公告)日:2009-04-23

    申请号:US12285481

    申请日:2008-10-07

    IPC分类号: G06F1/08

    摘要: A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.

    摘要翻译: 除了具有主CPU的主微型计算机之外,还配置有具有子CPU和控制对主微型计算机的电力供应的电源控制部的子微型计算机。 向子微型计算机提供具有较低频率的子时钟信号的子时钟部分可以在连续模式和间歇模式之间切换。 当主CPU向子CPU发出操作停止通知时,子CPU识别通知,停止对主微型计算机的供电,并将子时钟部分设置为间歇模式。 子CPU确定在间歇模式的周期内操作状态条件满足,子CPU将副时钟部分切换为连续模式,以重新开始向主微型计算机供电。

    Microcomputer system with reduced power consumption
    2.
    发明授权
    Microcomputer system with reduced power consumption 有权
    微电脑系统功耗降低

    公开(公告)号:US08046615B2

    公开(公告)日:2011-10-25

    申请号:US12285481

    申请日:2008-10-07

    IPC分类号: G06F1/32 G06F1/04

    摘要: A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.

    摘要翻译: 除了具有主CPU的主微型计算机之外,还配置有具有子CPU和控制对主微型计算机的电力供应的电源控制部的子微型计算机。 向子微型计算机提供具有较低频率的子时钟信号的子时钟部分可以在连续模式和间歇模式之间切换。 当主CPU向子CPU发出操作停止通知时,子CPU识别通知,停止对主微型计算机的供电,并将子时钟部分设置为间歇模式。 子CPU确定在间歇模式的周期内操作状态条件满足,子CPU将副时钟部分切换为连续模式,以重新开始向主微型计算机供电。

    Semiconductor memory device
    3.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US20090244956A1

    公开(公告)日:2009-10-01

    申请号:US12382875

    申请日:2009-03-26

    申请人: Akimitsu Inoue

    发明人: Akimitsu Inoue

    IPC分类号: G11C11/00 G11C5/14

    CPC分类号: G11C11/413

    摘要: In a memory cell, a margin for data preservation is provided while suppressing a current consumption associated with a low-power consumption mode. A MOS transistor has the same structure as NMOS transistors included in each of memory cells. When a low-power consumption mode is designated, a voltage developed at a node is stabilized by subtracting a margin voltage for data preservation across a first resistor from a voltage applied to a first node and by subtracting a threshold voltage of the MOS transistor from the resultant voltage is applied to a second node.

    摘要翻译: 在存储单元中,提供用于数据保存的余量,同时抑制与低功耗模式相关联的电流消耗。 MOS晶体管具有与每个存储单元中包括的NMOS晶体管相同的结构。 当指定低功耗模式时,通过从施加到第一节点的电压减去用于跨第一电阻器的数据保存的余量电压,并且通过从第一节点减去MOS晶体管的阈值电压来稳定在节点处产生的电压 合成电压被施加到第二节点。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US08085579B2

    公开(公告)日:2011-12-27

    申请号:US12382875

    申请日:2009-03-26

    申请人: Akimitsu Inoue

    发明人: Akimitsu Inoue

    IPC分类号: G11C11/00

    CPC分类号: G11C11/413

    摘要: In a memory cell, a margin for data preservation is provided while suppressing a current consumption associated with a low-power consumption mode. A MOS transistor has the same structure as NMOS transistors included in each of memory cells. When a low-power consumption mode is designated, a voltage developed at a node is stabilized by subtracting a margin voltage for data preservation across a first resistor from a voltage applied to a first node and by subtracting a threshold voltage of the MOS transistor from the resultant voltage is applied to a second node.

    摘要翻译: 在存储单元中,提供用于数据保存的余量,同时抑制与低功耗模式相关联的电流消耗。 MOS晶体管具有与每个存储单元中包括的NMOS晶体管相同的结构。 当指定低功耗模式时,通过从施加到第一节点的电压减去用于跨第一电阻器的数据保存的余量电压,并且通过从第一节点减去MOS晶体管的阈值电压来稳定在节点处产生的电压 合成电压被施加到第二节点。