公开(公告)号：US20080265278A1

公开(公告)日：2008-10-30

申请号：US12103911

申请日：2008-04-16

申请人： Kenji Hara ,  Junichi Sakano ,  Shinji Shirakawa

发明人： Kenji Hara ,  Junichi Sakano ,  Shinji Shirakawa

IPC分类号： H01L29/739 ,  G09G5/00

CPC分类号： H01L29/7394 ,  G09G3/293 ,  G09G3/296 ,  G09G2330/04

摘要： A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.

摘要翻译： 一种横向IGBT结构，其具有包括两个或更多个用于一个集电极端子的第二导电类型的基底层的发射极端子，其中发射极区域中的第二导电类型的基极层被第一导电类型层覆盖，所述第一导电类型层具有 浓度高于漂移层的浓度，使得覆盖发射极区域的第一导电类型层和掩埋氧化物膜之间的硅层具有降低的电阻，从而增加流向离集电极更远的发射极的电流，从而提高电流密度 。

公开(公告)号：US08384124B2

公开(公告)日：2013-02-26

申请号：US12707884

申请日：2010-02-18

申请人： Kenji Hara ,  Junichi Sakano ,  Shinji Shirakawa

发明人： Kenji Hara ,  Junichi Sakano ,  Shinji Shirakawa

IPC分类号： H01L29/02

CPC分类号： H01L29/7394 ,  G09G3/296 ,  G09G2330/04 ,  H01L27/0248

摘要： The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.

摘要翻译： 输出电路使用包含正常闩锁操作措施的IGBT，并且ESD钳位电路使用可以比具有防止闩锁的层的输出电路器件更容易闩锁的IGBT，该输出电路器件的杂质密度降低或去除。

公开(公告)号：US07875509B2

公开(公告)日：2011-01-25

申请号：US12103921

申请日：2008-04-16

申请人： Junichi Sakano ,  Kenji Hara ,  Shinji Shirakawa ,  Taiga Arai ,  Mutsuhiro Mori

发明人： Junichi Sakano ,  Kenji Hara ,  Shinji Shirakawa ,  Taiga Arai ,  Mutsuhiro Mori

IPC分类号： H01L21/84

CPC分类号： H01L29/7394 ,  H01L29/0878 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7824

摘要： In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm−3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.

摘要翻译： 在通过绝缘膜形成在支撑基板上的SOI型高耐受电压半导体器件的制造方法中，通过将杂质引入p型或者p型的整个表面来制造具有小耐受电压的小分散的小型半导体器件 n型SOI衬底，其杂质浓度为2E14cm-3或更小，并且用离子注入方法用作半导体器件的有源层，从而形成漂移层。

公开(公告)号：US20090315072A1

公开(公告)日：2009-12-24

申请号：US12487299

申请日：2009-06-18

申请人： Shinji Shirakawa ,  Junichi Sakano ,  Kenji Hara

发明人： Shinji Shirakawa ,  Junichi Sakano ,  Kenji Hara

IPC分类号： H01L29/739

CPC分类号： H01L29/7394 ,  H01L29/0696

摘要： In a lateral IGBT structure equipped with an emitter terminal, comprising two or more second conductivity type base layers, per one collector terminal, the second conductivity type base layer in the emitter region is covered by a first conductivity type layer which has a higher impurity concentration than the drift layer, and width L1 of the gate electrode located between two adjacent emitters is 4 μm or less, or in addition to that, width L2 of the opening for leading out an emitter electrode located between two adjacent gate electrodes is 3 μm or less.

摘要翻译： 在具有发射极端子的横向IGBT结构中，每个集电极端子包括两个或更多个第二导电型基极层，发射极区域中的第二导电类型基极层被具有较高杂质浓度的第一导电型层覆盖 位于两个相邻的发射极之间的栅电极的宽度L1为4μm以下，或者除此以外，用于引出位于两个相邻的栅电极之间的发射电极的开口的宽度L2为3μm或 减。

公开(公告)号：US07948058B2

公开(公告)日：2011-05-24

申请号：US12103911

申请日：2008-04-16

申请人： Kenji Hara ,  Junichi Sakano ,  Shinji Shirakawa

发明人： Kenji Hara ,  Junichi Sakano ,  Shinji Shirakawa

IPC分类号： H01L29/00

CPC分类号： H01L29/7394 ,  G09G3/293 ,  G09G3/296 ,  G09G2330/04

摘要： A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.

摘要翻译： 一种横向IGBT结构，其具有包括两个或更多个用于一个集电极端子的第二导电类型的基底层的发射极端子，其中发射极区域中的第二导电类型的基极层被第一导电类型层覆盖，所述第一导电类型层具有 浓度高于漂移层的浓度，使得覆盖发射极区域的第一导电类型层和掩埋氧化物膜之间的硅层具有降低的电阻，从而增加流向离集电极更远的发射极的电流，从而提高电流密度 。

公开(公告)号：US20100165681A1

公开(公告)日：2010-07-01

申请号：US12646990

申请日：2009-12-24

申请人： Junichi Sakano ,  Kenji Hara ,  Shinji Shirakawa

发明人： Junichi Sakano ,  Kenji Hara ,  Shinji Shirakawa

IPC分类号： H02M7/06 ,  H03K17/687

CPC分类号： H03K17/163 ,  H03K17/6877

摘要： In a driving circuit, for controlling the turning on and off of a main semiconductor switching device of an insulated gate type, in an insulated gate semiconductor switching device for electric power conversion, bipolar semiconductor devices of an insulated gate control type, particularly insulated gate bipolar transistors (IGBTs) are used at the output stage of a circuit that controls the gate voltage of the main semiconductor switching device.

摘要翻译： 在用于控制绝缘栅型主半导体开关器件的导通和截止的驱动电路中，在用于电力转换的绝缘栅半导体开关器件中，绝缘栅极控制型双极半导体器件，特别是绝缘栅极双极型 在控制主半导体开关器件的栅极电压的电路的输出级使用晶体管（IGBT）。

公开(公告)号：US08487343B2

公开(公告)日：2013-07-16

申请号：US12825839

申请日：2010-06-29

申请人： Shinji Shirakawa ,  Junichi Sakano ,  Kenji Hara

发明人： Shinji Shirakawa ,  Junichi Sakano ,  Kenji Hara

IPC分类号： H01L29/739

CPC分类号： H01L29/7394 ,  H01L29/0696

摘要： A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.

摘要翻译： 形成在SOI衬底上的具有大电流密度的水平型IGBT具有发射极区域，其在氧化物膜沟槽上由二（2）个或更多个第二导电类型的基底层构成 其特征在于，所述发射极区域中的所述第二导电型的基极层被覆盖有比漂移层高的导电性的第一导电型层，所述氧化物膜沟槽上的栅电极的长度为 比集电体上的栅电极的长度小，并且在集电体上形成第二导电类型的基底层下方的第一导电型高密度层，从而实现层间的高密度化 第一导电型，同时保持耐久电压，并增加电流密度。

公开(公告)号：US20100219448A1

公开(公告)日：2010-09-02

申请号：US12707884

申请日：2010-02-18

申请人： Kenji HARA ,  Junichi Sakano ,  Shinji Shirakawa

发明人： Kenji HARA ,  Junichi Sakano ,  Shinji Shirakawa

IPC分类号： H01L29/739

CPC分类号： H01L29/7394 ,  G09G3/296 ,  G09G2330/04 ,  H01L27/0248

摘要： The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.

摘要翻译： 输出电路使用包含正常闩锁操作措施的IGBT，并且ESD钳位电路使用可以比具有防止闩锁的层的输出电路器件更容易闩锁的IGBT，该输出电路器件的杂质密度降低或去除。

公开(公告)号：US20080265331A1

公开(公告)日：2008-10-30

申请号：US12103921

申请日：2008-04-16

申请人： Junichi Sakano ,  Kenji Hara ,  Shinji Shirakawa ,  Taiga Arai ,  Mutsuhiro Mori

发明人： Junichi Sakano ,  Kenji Hara ,  Shinji Shirakawa ,  Taiga Arai ,  Mutsuhiro Mori

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： H01L29/7394 ,  H01L29/0878 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7824

摘要： In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm−3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.

摘要翻译： 在通过绝缘膜形成在支撑基板上的SOI型高耐受电压半导体器件的制造方法中，通过将杂质引入p型或者p型的整个表面来制造具有小耐受电压的小分散的小型半导体器件 n型SOI衬底，其杂质浓度为2E14cm -3或更小，并且用离子注入方法用作半导体器件的有源层，从而形成漂移层。

公开(公告)号：US07126308B2

公开(公告)日：2006-10-24

申请号：US10715379

申请日：2003-11-19

申请人： Satoru Shigeta ,  Yuuji Maeda ,  Junichi Sakano ,  Shinji Shirakawa

发明人： Satoru Shigeta ,  Yuuji Maeda ,  Junichi Sakano ,  Shinji Shirakawa

IPC分类号： H02P27/04

CPC分类号： H03K17/163 ,  H03K17/16

摘要： In order to provide an interface circuit, a power converter using the same and an electric vehicle using the same, wherein this interface circuit ensures improved control reliability without employing a photo-coupler, an interface circuit 100A transfers control signals to the power transistor in a large-current circuit 300 from a small-signal circuit 200 for driving a power transistor. The interface circuit 100A has a noise absorber 120 that electrically absorbs a noise voltage produced between the ground of the small-signal circuit 200 and that of the power transistor. The noise absorber 120 transfers to the power transistor the control signals generated by the small-signal circuit 200, without being affected by the noise voltage if produced.

摘要翻译： 为了提供接口电路，使用该接口电路的电力转换器和使用该接口电路的电动车辆，其中该接口电路确保在不使用光电耦合器的情况下改善控制可靠性，接口电路100A将控制信号传送到功率晶体管 来自用于驱动功率晶体管的小信号电路200的大电流电路300。 接口电路100A具有电吸收小信号电路200的接地与功率晶体管的接地之间产生的噪声电压的噪声吸收体120。 噪声吸收器120将由小信号电路200产生的控制信号传送到功率晶体管，而不受噪声电压的影响。