摘要:
The PDP has front plate and a rear plate. Front plate and the rear plate are oppositely disposed and sealed at the peripheries. Front plate has display electrode and dielectric layer. Dielectric layer contains an oxide of a divalent element, an oxide of a trivalent element, and an oxide of a tetravalent element. The total content of the oxide of a trivalent element and the oxide of a tetravalent element is larger by weight than the content of the oxide of a divalent element.
摘要:
A plasma display panel includes a front plate and a rear plate disposed in such a manner as to face the front plate. The front plate has a display electrode and a dielectric layer covering the display electrode. The dielectric layer contains substantially no lead components but contains MgO, SiO2, and K2O. A content of MgO is in a range between 0.3 mol % and 1.0 mol %, both inclusive. The content of SiO2 is in a range between 35 mol % and 50 mol %, both inclusive.
摘要:
A plasma display panel includes a front plate and a rear plate disposed in such a manner as to face the front plate. The front plate has a display electrode and a dielectric layer covering the display electrode. The dielectric layer contains substantially no lead components but contains MgO, SiO2, and K2O. A content of MgO is in a range between 0.3 mol % and 1.0 mol %, both inclusive. The content of SiO2 is in a range between 35 mol % and 50 mol %, both inclusive.
摘要:
An aligning and feeding device capable of reliably aligning objects having a plane shape with an unequal ratio of length to width longitudinally and feeding them is provided.An aligning and feeding device has a rotary table 2 horizontally rotatable, drive means 3 for rotating the rotary table 2, a supply mechanism for supplying objects to be aligned onto the rotary table 2 and a guide mechanism 7 for defining a conveying path for the objects to be aligned conveyed by the rotary table 2. The guide mechanism 7 has an introduction guide 11, first pair of alignment guides 16, second pair of alignment guides 19 and pair of discharge guides 23 which each has a guide face and are disposed sequentially along the conveying path for the objects to be aligned. The first pair of alignment guides 16 and the second pair of alignment guides 19 each have an outer guide positioned so that a start point of its guide face is closer to the periphery of the rotary table 2 than an end point thereof, and an inner guide positioned so that a start point of its guide face is closer to the center of the rotary table 2 than an end point thereof.
摘要:
A buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied. A buffer circuit with driving current adjusting function of the present invention comprises a buffer circuit which is controlled by a control signal for supplying a most appropriate driving current to a load; a load detecting circuit for detecting a phase difference between an input signal and an output signal of the buffer circuit and for outputting voltage corresponding to the phase difference, a control signal generating circuit for generating a signal which controls the driving current of the buffer circuit in response to an output signal of the load detecting circuit, the control signal controls so that the driving current of buffer circuit is increased when delay time of buffer circuit becomes long and the driving current of buffer circuit is decreased when delay time becomes short.
摘要:
A memory card connector assembly superimposed on a substrate includes a plurality of memory card connectors stacked on top of each other whose contacts are to be connected to corresponding terminals of associated memory cards. The contacts of a lowermost memory card connector are soldered to the substrate, and the contacts of at least one upper memory card connector are connected to an FPC board.
摘要:
A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要:
PD detects a phase difference between DATA and VDL output from VDL. Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of VDL exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by PD, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要:
A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要:
A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.