公开(公告)号：US08175205B2

公开(公告)日：2012-05-08

申请号：US12883272

申请日：2010-09-16

申请人： Masashi Ishii ,  Takanori Hirota ,  Atsuhiko Ishibashi ,  Yasushi Hayakawa ,  Takeshi Oshita ,  Yoshiyuki Ota

发明人： Masashi Ishii ,  Takanori Hirota ,  Atsuhiko Ishibashi ,  Yasushi Hayakawa ,  Takeshi Oshita ,  Yoshiyuki Ota

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/087

摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

摘要翻译： 相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。 代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。 然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于 一次等于输出时钟的一个周期的延迟与控制码相加或相减。 因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

公开(公告)号：US20070018704A1

公开(公告)日：2007-01-25

申请号：US11477597

申请日：2006-06-30

申请人： Masashi Ishii ,  Takanori Hirota ,  Atsuhiko Ishibashi ,  Yasushi Hayakawa ,  Takeshi Oshita ,  Yoshiyuki Ota

发明人： Masashi Ishii ,  Takanori Hirota ,  Atsuhiko Ishibashi ,  Yasushi Hayakawa ,  Takeshi Oshita ,  Yoshiyuki Ota

IPC分类号： H03K5/01

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/087

摘要： PD detects a phase difference between DATA and VDL output from VDL. Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of VDL exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by PD, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

摘要翻译： PD检测VDL与DATA与VDL输出之间的相位差。 代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。 然后，当根据PD的检测结果改变控制码时，当输出时钟与数据信号同步期间，当VDL的延迟量超过时钟的一个周期时，对应于等于一个周期的延迟的控制码 的输出时钟被一次添加到/从控制码中减去。 因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

公开(公告)号：US20110007855A1

公开(公告)日：2011-01-13

申请号：US12883272

申请日：2010-09-16

申请人： Masashi Ishii ,  Takanori Hirota ,  Atsuhiko Ishibashi ,  Yasushi Hayakawa ,  Takeshi Oshita ,  Yoshiyuki Ota

发明人： Masashi Ishii ,  Takanori Hirota ,  Atsuhiko Ishibashi ,  Yasushi Hayakawa ,  Takeshi Oshita ,  Yoshiyuki Ota

IPC分类号： H04L7/04

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/087

摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

摘要翻译： 相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。 代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。 然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于 一次等于输出时钟的一个周期的延迟与控制码相加或相减。 因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

公开(公告)号：US07822158B2

公开(公告)日：2010-10-26

申请号：US11477597

申请日：2006-06-30

申请人： Masashi Ishii ,  Takanori Hirota ,  Atsuhiko Ishibashi ,  Yasushi Hayakawa ,  Takeshi Oshita ,  Yoshiyuki Ota

发明人： Masashi Ishii ,  Takanori Hirota ,  Atsuhiko Ishibashi ,  Yasushi Hayakawa ,  Takeshi Oshita ,  Yoshiyuki Ota

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/087

摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

摘要翻译： 相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。 代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。 然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于 一次等于输出时钟的一个周期的延迟与控制码相加或相减。 因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

公开(公告)号：US06861883B2

公开(公告)日：2005-03-01

申请号：US10360754

申请日：2003-02-10

申请人： Takanori Hirota ,  Atsuhiko Ishibashi

发明人： Takanori Hirota ,  Atsuhiko Ishibashi

IPC分类号： H03K5/00 ,  H03K5/13 ,  H03K19/0175 ,  H03L7/00 ,  H03L7/06 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087 ,  H03L7/099 ,  H03L7/22

CPC分类号： H03K5/133 ,  H03K2005/00071 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0996

摘要： Assuming that clocks in an A clock driver (102), a B clock driver (103) and a CMOS buffer circuit (119) have delay values Ta, Tb and Td, respectively, a delay value Ta−Td is stored in a register circuit (117) when terminals “0” of selector circuits (114, 115, 116) are selected, and a delay value Ta−Td−Tb is stored in a register circuit (118) when the terminals “0” are switched to “1”. Thus, determining a delay value at the CMOS buffer circuit (119) allows a phase difference between the A clock driver (102) and B clock driver (103) to be determined.

摘要翻译： 假设A时钟驱动器（102），B时钟驱动器（103）和CMOS缓冲电路（119）中的时钟分别具有延迟值Ta，Tb和Td，延迟值Ta-Td被存储在寄存器电路 当选择器电路（114,115,116）的端子“0”被选择时，当端子“0”被切换到“1”时，延迟值Ta-Td-Tb被存储在寄存器电路（118）中， “。 因此，确定CMOS缓冲电路（119）的延迟值允许确定A时钟驱动器（102）和B时钟驱动器（103）之间的相位差。

公开(公告)号：US08723367B2

公开(公告)日：2014-05-13

申请号：US13011526

申请日：2011-01-21

申请人： Atsuhiko Ishibashi

发明人： Atsuhiko Ishibashi

IPC分类号： H01F37/00

CPC分类号： H02J50/12 ,  H02J5/005

摘要： In a power supply system, reducing influence of a noise etc., optimal electric power is supplied corresponding to power consumption of a receiving side load, and power consumption is decreased greatly. When a potential difference detector 12 detects that a power supply voltage of the receiving side load is decreased lower than a lower limit voltage threshold or increased higher than an upper limit voltage threshold, a burst interval setting unit sets up a burst signal of a pulse width corresponding to the detection result. A burst signal generator generates a burst signal based on the setup, and excites a control primary inductor. A burst signal detector generates a pulse signal in response to electromotive force of a control secondary inductor. A pulse width controller determines increase or decrease of the voltage value of the receiving side load from a no-signal period of a pulse signal, measured by a no-signal period measuring unit, and modifies and outputs a signal outputted by a alternating current generator so as to change a period or the number of times to excite a power primary inductor.

摘要翻译： 在电源系统中，减小噪声的影响等，根据接收侧的负载的功率消耗来提供最优的电力，大大降低功耗。 当电位差检测器12检测到接收侧负载的电源电压降低到比下限电压阈值低或者高于上限电压阈值时，突发间隔设置单元设置脉冲宽度的脉冲串信号 对应于检测结果。 突发信号发生器基于设置产生脉冲串信号，并激励控制主电感器。 突发信号检测器响应于控制次级电感器的电动势产生脉冲信号。 脉冲宽度控制器从由无信号周期测量单元测量的脉冲信号的无信号周期确定接收侧负载的电压值的增加或减小，并且修改并输出由交流发电机输出的信号 以便改变激励电源初级电感器的周期或次数。

公开(公告)号：US20050110526A1

公开(公告)日：2005-05-26

申请号：US10900312

申请日：2004-07-28

申请人： Atsuhiko Ishibashi ,  Yasuhiro Fujino

发明人： Atsuhiko Ishibashi ,  Yasuhiro Fujino

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/317 ,  G06F1/04 ,  H03K3/037 ,  H03K5/19 ,  H04L25/02

CPC分类号： G01R31/025 ,  G01R31/317 ,  H03K3/037

摘要： Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal. Thereby, if a second D-flip-flop circuit F2a negates an output signal [CD], it is able to judge that disconnection or short occurs.

摘要翻译： 提供了能够检测发送差分时钟信号的信号线的断开和短路的断开和短路检测电路。 差分缓冲器部分DB1具有第一比较器，用于比较从PADI输入的非反相时钟信号和从PADR输入的反相时钟信号; 第二比较器，用于比较非反相时钟信号和参考电位Vref; 以及比较反相时钟信号和参考电位Vref的第三比较器。 它们各自的输出分别定义为Y，YI和YR。 如果非反相时钟信号或反相时钟信号的信号线断开或短路到逻辑值Low的接地电位VSS，则从第二和第三比较器输出的逻辑值对于 长时间在一个周期的非反相时钟信号或反相时钟信号。 因此，如果第二D触发器电路F 2 a否定输出信号[CD]，则能够判断出断开或短路。

公开(公告)号：US06714083B2

公开(公告)日：2004-03-30

申请号：US10131219

申请日：2002-04-25

申请人： Atsuhiko Ishibashi

发明人： Atsuhiko Ishibashi

IPC分类号： H03L700

CPC分类号： H03L7/0891 ,  H03L7/095 ,  H03L7/18

摘要： There are provided a lock detector that does not output a lock detecting signal of incorrect content even when approaching phase synchronization, when an input signal stops suddenly, or when a phase difference becomes zero momentarily in the progress that an output signal is synchronized with an input signal, as well as a PLL circuit including this lock detector. Specifically, a PLL circuit includes a lock detector (20) which comprises a reset signal output part (6, 7, 22 to 24) that outputs a reset signal (Pe) upon a phase difference between an input signal (f1) and a feedback signal (f2); and a D-FF circuit (8) that does not output a lock detecting signal (SL) upon receipt of the reset signal. The feedback signal (f2) is inputted to an NAND circuit (23) such that the reset signal is also based on the signal change of the feedback signal (f2). Further, a counter (21) performing output when the input signal (f1) reaches N-cycle is used for the clock of the D-FF circuit (8).

摘要翻译： 即使在接近相位同步，输入信号突然停止时，或当输出信号与输入同步的进行中相位差变为零时，也不会输出不正确内容的锁定检测信号的锁定检测器 信号，以及包括该锁定检测器的PLL电路。 具体地说，PLL电路包括锁定检测器（20），该锁定检测器包括复位信号输出部分（6,7,22至24），该复位信号输出部分根据输入信号（f1）和反馈信号之间的相位差输出复位信号（Pe） 信号（f2）; 以及在接收到复位信号时不输出锁定检测信号（SL）的D-FF电路（8）。 反馈信号（f2）输入到NAND电路（23），使得复位信号也基于反馈信号（f2）的信号变化。 此外，当D-FF电路（8）的时钟使用当输入信号（f1）达到N周期时执行输出的计数器（21）。

公开(公告)号：US5420544A

公开(公告)日：1995-05-30

申请号：US130727

申请日：1993-10-04

申请人： Atsuhiko Ishibashi

发明人： Atsuhiko Ishibashi

IPC分类号： H01L27/118 ,  G06F1/10 ,  G11C11/401 ,  G11C11/407 ,  H01L21/82 ,  H03L7/08 ,  H03L7/087 ,  H03L7/089 ,  H03L7/00

CPC分类号： G06F1/10 ,  H03L7/087 ,  H03L7/0891

摘要： A skew due to distribution of a clock inside a gate array is reduced. Phase comparators (14A), (14B) and (14C) are prepared in the peripheral portion of an internal circuit 71. The phase comparator (14C) is selected which is located nearest an element (77C) which receives an internal clock signal (65C) which is to be synchronized in terms of phase with an external clock signal (73). The selected phase comparator (14C) is connected to a charge pump circuit (16). Without forming a plurality of PLL circuits except for the phase comparators, the phase of any desired internal clock signal is synchronized with the phase of the external clock signal.

摘要翻译： 由于门阵列内的时钟分布引起的偏斜减少。 相位比较器（14A），（14B）和（14C）被准备在内部电路71的外围部分中。选择位于最接近元件（77C）的相位比较器（14C），该元件接收内部时钟信号（65C ），其将与外部时钟信号（73）在相位方面进行同步。 所选择的相位比较器（14C）连接到电荷泵电路（16）。 除了相位比较器之外，不形成多个PLL电路，任何期望的内部时钟信号的相位与外部时钟信号的相位同步。

公开(公告)号：US5347233A

公开(公告)日：1994-09-13

申请号：US40314

申请日：1993-03-30

申请人： Atsuhiko Ishibashi ,  Harufusa Kondoh ,  Masaya Kitao

发明人： Atsuhiko Ishibashi ,  Harufusa Kondoh ,  Masaya Kitao

IPC分类号： H03L7/095 ,  H03L7/087 ,  H03L7/089 ,  H03L7/107 ,  H03L7/113 ,  H03L7/00

CPC分类号： H03L7/107 ,  H03L7/0891 ,  H03L7/113

摘要： A PLL circuit apparatus in accordance with the present invention includes a phase comparator, a delay circuit, a NOR circuit, and a loop filter. The phase comparator detects a phase difference between a reference clock signal and an internal clock signal. The delay circuit delays the reference clock signal by a delay time of an output of the phase comparator. The NOR circuit determines which pulse width is larger of a phase difference detecting signal from the phase comparator or of the delayed reference clock signal. The loop filter has its gain changed in response to an output of the NOR circuit. Thus, it is possible to shorten a synchronization pull-in time and accurately detect a deviation in synchronization. In addition, if a gain control signal is reset on the basis of logic states of a reference clock signal and an internal clock signal in accordance with rising edges and falling edges of the clock signals, it is possible to generate successive gain control signals.

摘要翻译： 根据本发明的PLL电路装置包括相位比较器，延迟电路，NOR电路和环路滤波器。 相位比较器检测参考时钟信号和内部时钟信号之间的相位差。 延迟电路将参考时钟信号延迟相位比较器的输出的延迟时间。 NOR电路确定来自相位比较器或延迟的参考时钟信号的相位差检测信号的哪个脉冲宽度较大。 环路滤波器的增益响应于NOR电路的输出而改变。 因此，可以缩短同步引入时间并精确地检测同步偏差。 此外，如果根据时钟信号的上升沿和下降沿基于参考时钟信号和内部时钟信号的逻辑状态来复位增益控制信号，则可以产生连续的增益控制信号。