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公开(公告)号：US20120120739A1
公开(公告)日：2012-05-17
申请号：US13356341
申请日：2012-01-23
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。
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公开(公告)号：US20100302879A1
公开(公告)日：2010-12-02
申请号：US12847955
申请日：2010-07-30
IPC分类号： G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。
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公开(公告)号：US20090016142A1
公开(公告)日：2009-01-15
申请号：US12234969
申请日：2008-09-22
IPC分类号： G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
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公开(公告)号：US20120331043A1
公开(公告)日：2012-12-27
申请号：US13527311
申请日：2012-06-19
IPC分类号： G06F15/16
CPC分类号： H04L67/1095 , H04L67/26 , H04L67/325 , H04L69/28
摘要： When data is disclosed to a plurality of users by using a transfer network and a transfer apparatus, data disclosure time control which cannot be adversely affected by the users is performed to reduce the difference in data disclosure time among the users. A transfer network system includes a distribution server serving as a data-distribution-source transfer apparatus, and a network terminal connected to distribution-destination user equipment. The distribution server and the network terminal each have a time keeping function and a time synchronization function for matching the time of the time keeping function with a master clock. The distribution server sends in advance disclosure data and disclosure time to the network terminal. When the time of the time keeping function of the network terminal matches the disclosure time, the network terminal sends the disclosure data to the user equipment.
摘要翻译： 当通过使用传送网络和传送装置向多个用户公开数据时，执行不受用户不利影响的数据公开时间控制，以减少用户之间的数据公开时间的差异。 传送网络系统包括用作数据分发源传送装置的分发服务器和连接到分发目的地用户设备的网络终端。 分发服务器和网络终端均具有时间保持功能和时间同步功能，用于将时间保持功能的时间与主时钟相匹配。 分发服务器预先向网络终端发送披露数据和公开时间。 当网络终端的时间保持功能与公布时间匹配时，网络终端向用户设备发送公开数据。
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5.发明申请公开(公告)号：US20090161468A1
公开(公告)日：2009-06-25
申请号：US12258970
申请日：2008-10-27
申请人： Shinya FUJIOKA
发明人： Shinya FUJIOKA
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615
摘要： A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal.
摘要翻译： 提供了一种半导体存储器，所述半导体存储器包括包括多个存储单元的存储器核心，产生用于刷新存储单元的刷新请求的刷新生成单元，响应于访问执行访问操作的核心控制单元 请求，等待时间确定单元，其在激活芯片使能信号和刷新请求之间的冲突时激活延迟扩展信号，并且响应于芯片使能信号的去激活而停用延迟扩展信号;等待时间输出缓冲器，其输出 延迟扩展信号，以及数据控制单元，其在等待时间延长信号的激活期间将等待时间从访问请求改变为数据传输到数据终端。
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公开(公告)号：US20090154257A1
公开(公告)日：2009-06-18
申请号：US12257799
申请日：2008-10-24
申请人： Shinya FUJIOKA , Yasuyuki Eguchi
发明人： Shinya FUJIOKA , Yasuyuki Eguchi
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C11/4074 , G11C2207/2227
摘要： The memory system comprises: a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage; a first control unit that includes a control input/output circuit, which is coupled to the memory input/output circuit and operates according to the second power supply voltage; a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal; a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal; and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.
摘要翻译： 所述存储器系统包括：半导体存储器，其包括根据第一电源电压工作的内部电路和存储器输入/输出电路，所述存储器输入/输出电路耦合到所述内部电路并根据第二电源电压进行操作; 第一控制单元，其包括控制输入/输出电路，其耦合到所述存储器输入/输出电路并根据所述第二电源电压进行操作; 电压产生单元，其产生第二电源电压并根据电压调节信号改变第二电源电压; 时钟发生单元，其产生时钟信号并根据时钟调整信号改变时钟信号的频率; 以及第二控制单元，其根据第一控制单元的半导体存储器的访问状态生成电压调整信号和时钟调整信号。
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