摘要:
When data is disclosed to a plurality of users by using a transfer network and a transfer apparatus, data disclosure time control which cannot be adversely affected by the users is performed to reduce the difference in data disclosure time among the users. A transfer network system includes a distribution server serving as a data-distribution-source transfer apparatus, and a network terminal connected to distribution-destination user equipment. The distribution server and the network terminal each have a time keeping function and a time synchronization function for matching the time of the time keeping function with a master clock. The distribution server sends in advance disclosure data and disclosure time to the network terminal. When the time of the time keeping function of the network terminal matches the disclosure time, the network terminal sends the disclosure data to the user equipment.
摘要:
A packet transport system to which the present invention is applied includes an edge node accommodating an access network at an edge, and a core node of carrying out a processing of assorting a frame gathered from a plurality of the edge nodes, the edge node provides a label to the frame flowing in from the access network, and the packet transport system transmits the frame in reference to the label. The edge node includes a priority information providing portion of changing a piece of priority information provided to the frame flowing in from the access network in accordance with a congested state of the core node, and a priority previously set to a path specified by the label.
摘要:
A packet transport system to which the present invention is applied includes an edge node accommodating an access network at an edge, and a core node of carrying out a processing of assorting a frame gathered from a plurality of the edge nodes, the edge node provides a label to the frame flowing in from the access network, and the packet transport system transmits the frame in reference to the label. The edge node includes a priority information providing portion of changing a piece of priority information provided to the frame flowing in from the access network in accordance with a congested state of the core node, and a priority previously set to a path specified by the label.
摘要:
A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.
摘要:
A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要:
An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要:
A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.
摘要:
A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.
摘要:
A dual-port semiconductor memory apparatus constructed by a core circuit and a plurality of ports, different row blocks of which in the same column block of the core circuit are simultaneously accessible. Since each of the ports is provided with a global data bus, different row blocks of the same column block can be accessed via both ports by selectively activating a column line corresponding to a port and another column line corresponding to another port.
摘要:
Operating margins of a semiconductor integrated circuit are reliably tested at low power consumption by switching power supply circuits between normal operation mode wherein a first step-up power supply serves both memory core and a step-down power supply, and testing mode wherein the memory core is powered by an external testing power supply that provides a fluctuating voltage for testing, and the step-down power supply is served by a second step-up power supply.