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7 条记录 (耗时 0.024 秒)

    HIGH-STRENGTH BRASS ALLOY FOR SLIDING MEMBERS, AND SLIDING MEMBERS
    1.
    发明申请
    HIGH-STRENGTH BRASS ALLOY FOR SLIDING MEMBERS, AND SLIDING MEMBERS 有权
    用于滑动构件的高强度铜合金和滑动构件

    公开(公告)号：US20120020600A1

    公开(公告)日：2012-01-26

    申请号：US13142502

    申请日：2010-01-06

    申请人： Shinya Nishimura ,  Tomoyuki Yamane ,  Takeshi Kondo

    发明人： Shinya Nishimura ,  Tomoyuki Yamane ,  Takeshi Kondo

    IPC分类号： F16C33/10 ,  C22C30/02 ,  C22C9/04

    CPC分类号： C22C9/04 ,  C22C30/06 ,  F16C33/1095 ,  F16C33/121 ,  F16C2202/52 ,  F16C2204/14 ,  F16C2204/50 ,  F16C2240/40

    摘要： A high-strength brass alloy for sliding members, consists of, by mass %, 17 to 28% of Zn, 5 to 10% of Al, 4 to 10% of Mn, 1 to 5% of Fe, 0.1 to 3% of Ni, 0.5 to 3% of Si, and the balance of Cu and inevitable impurities. The high-strength brass alloy has a structure that includes a matrix of a single phase structure of the β phase and includes at least one of Fe—Mn—Si intermetallic compounds in the form of aciculae, spheres, or petals dispersed in the β phase.

    摘要翻译： 用于滑动构件的高强度黄铜合金以质量％计含有17至28％的Zn，5至10％的Al，4至10％的Mn，1至5％的Fe，0.1至3％的 Ni，0.5〜3％的Si，余量为Cu和不可避免的杂质。 高强度黄铜合金具有包括单相结构的基体的结构。 相，并且包括分散在所述组合物中的尖头，球形或花瓣形式的至少一种Fe-Mn-Si金属间化合物; 相。

    Measuring apparatus, measuring method, and test apparatus
    5.
    发明授权
    Measuring apparatus, measuring method, and test apparatus 有权
    测量装置，测量方法和测试装置

    公开(公告)号：US07262627B2

    公开(公告)日：2007-08-28

    申请号：US11497506

    申请日：2006-08-01

    申请人： Tomoyuki Yamane ,  Hirokatsu Niijima

    发明人： Tomoyuki Yamane ,  Hirokatsu Niijima

    IPC分类号： G01R31/26

    CPC分类号： G01R29/26

    摘要： There is provided a measuring apparatus that generates a first strobe signal and a second strobe signal in synchronization with an output signal, sequentially changes phases of the strobe signals whenever the electronic device outputs the output signal multiple times, acquires a signal level of the output signal at each phase of the strobe signals by the multiple times, counts the number of times by which the signal level of the output signal to the first strobe signal is a High level for each phase of the first strobe signal, counts the number of times by which the signal level of the output signal to the second strobe signal is a Low level for each phase of the second strobe signal, and computes a phase of a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter based on the counted number of times. The measuring apparatus measures a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter by one-time test.

    摘要翻译： 提供了一种与输出信号同步地产生第一选通信号和第二选通信号的测量装置，每当电子设备多次输出输出信号时，依次改变选通信号的相位，获取输出信号的信号电平 在多次选通信号的每个相位，计数第一选通信号的输出信号的信号电平对于第一选通信号的每个相位为高电平的次数，将次数计数 其中第二选通信号的输出信号的信号电平为第二选通信号的每个相位的低电平，并且计算输出信号的波形的变化点，抖动量和抖动分布的相位 基于计数次数。 测量装置通过一次性测试来测量输出信号的波形的变化点，抖动量和抖动分布。

    Semiconductor memory test apparatus and method for address generation for defect analysis
    6.
    发明授权
    Semiconductor memory test apparatus and method for address generation for defect analysis 有权
    用于缺陷分析的地址产生的半导体存储器测试装置和方法

    公开(公告)号：US07240256B2

    公开(公告)日：2007-07-03

    申请号：US10477782

    申请日：2002-05-16

    申请人： Tomoyuki Yamane

    发明人： Tomoyuki Yamane

    IPC分类号： G11C29/04 ,  G01R31/3183

    CPC分类号： G11C29/56004 ,  G11C29/26 ,  G11C29/56 ,  G11C2029/5606

    摘要： There is disclosed a semiconductor memory test apparatus capable of easily generating an address to be input into a failure analysis memory for testing a memory device having a burst function which automatically generates addresses for banks therein. Each of registers corresponding to the banks of the memory device holds a line address of the corresponding bank. When a start address of one of the banks is input to the memory device, a line address of the same bank as the start address is read out from the register corresponding to the bank and output to a failure analysis memory together with the start address. Furthermore, during burst operation of the bank, the registers output the line address to the failure analysis memory together the same line address as the memory device generated by calculating the start address for each clock cycle.

    摘要翻译： 公开了一种半导体存储器测试装置，其能够容易地产生要输入到故障分析存储器中的地址，以测试具有自动生成其中的存储体的地址的突发功能的存储器件。 与存储装置的存储体相对应的每个寄存器保存相应存储体的行地址。 当其中一个存储体的起始地址被输入到存储器件时，与对应于存储体的寄存器中读出与起始地址相同的存储体的行地址，并与起始地址一起输出到故障分析存储器。 此外，在存储体的突发操作期间，寄存器将故障分析存储器的行地址输出到与通过计算每个时钟周期的起始地址产生的存储器件相同的行地址。

    Measuring apparatus, measuring method, and test apparatus
    7.
    发明申请
    Measuring apparatus, measuring method, and test apparatus 有权

    公开(公告)号：US20070096762A1

    公开(公告)日：2007-05-03

    申请号：US11497506

    申请日：2006-08-01

    申请人： Tomoyuki Yamane ,  Hirokatsu Niijima

    发明人： Tomoyuki Yamane ,  Hirokatsu Niijima

    IPC分类号： G01R31/26

    CPC分类号： G01R29/26

    摘要： There is provided a measuring apparatus that generates a first strobe signal and a second strobe signal in synchronization with an output signal, sequentially changes phases of the strobe signals whenever the electronic device outputs the output signal multiple times, acquires a signal level of the output signal at each phase of the strobe signals by the multiple times, counts the number of times by which the signal level of the output signal to the first strobe signal is a High level for each phase of the first strobe signal, counts the number of times by which the signal level of the output signal to the second strobe signal is a Low level for each phase of the second strobe signal, and computes a phase of a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter based on the counted number of times. The measuring apparatus measures a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter by one-time test.