公开(公告)号：US6114917A

公开(公告)日：2000-09-05

申请号：US181617

申请日：1998-10-28

申请人： Shoj Nakajima ,  Tamami Hatanaka ,  Moriyuki Tashiro ,  Minoru Kiumi ,  Hirohisa Hirano

发明人： Shoj Nakajima ,  Tamami Hatanaka ,  Moriyuki Tashiro ,  Minoru Kiumi ,  Hirohisa Hirano

IPC分类号： H03K3/03 ,  H03K3/354 ,  H03L7/083 ,  H03L7/099 ,  H03L7/10 ,  H03L7/199 ,  H03B5/00 ,  H03L7/09

CPC分类号： H03L7/199 ,  H03L7/083 ,  H03L7/0995 ,  H03L7/10

摘要： The present invention provides an analog PLL circuit able to shorten a lockin time during which oscillating frequency and phase of a voltage controlling oscillator settle.An analog PLL circuit according to the present invention comprises a divider, a phase comparator, a charge pump, a low pass filter, a voltage controlling oscillator, and a divider. The voltage controlling oscillator has a ring oscillator composed of a plurality of logic inverting elements capable of changing the delay amount. During the reset period, the initial voltage is inputted to the voltage controlling oscillator via the analog switch, and the initial delay amount is set to each of the logic inverting elements. After the reset period finishes, at the point when the rising edge of the standard input signal is firstly inputted, the output of the D flip-flop becomes high level and the ring oscillator begins the oscillating operation.

摘要翻译： 本发明提供一种能够缩短锁定时间的模拟PLL电路，在此时间内，电压控制振荡器的振荡频率和相位稳定。 根据本发明的模拟PLL电路包括分频器，相位比较器，电荷泵，低通滤波器，电压控制振荡器和分频器。 电压控制振荡器具有由能够改变延迟量的多个逻辑反相元件组成的环形振荡器。 在复位期间，初始电压通过模拟开关输入到电压控制振荡器，并且将初始延迟量设置到每个逻辑反相元件。 复位周期结束后，在首次输入标准输入信号的上升沿时，D触发器的输出变为高电平，环形振荡器开始振荡。