公开(公告)号：US20190278513A1

公开(公告)日：2019-09-12

申请号：US16422827

申请日：2019-05-24

申请人： Shrinivas Venkatraman ,  Eng Hun Ooi ,  Sahar Khalili ,  Dimpesh Patel ,  Kuan Hua Tan

发明人： Shrinivas Venkatraman ,  Eng Hun Ooi ,  Sahar Khalili ,  Dimpesh Patel ,  Kuan Hua Tan

IPC分类号： G06F3/06 ,  G06F13/42

摘要： Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.

公开(公告)号：US20130283085A1

公开(公告)日：2013-10-24

申请号：US13977500

申请日：2011-12-22

申请人： Shrinivas Venkatraman

发明人： Shrinivas Venkatraman

IPC分类号： G06F1/10

CPC分类号： G06F1/10 ,  G06F13/00 ,  G06F13/4221 ,  G06K5/04

摘要： A method and apparatus to deskew dead cycles is described using a block aligner. In one example a method includes receiving a sequence of bytes into a first buffer from each lane of a multiple lane peripheral device bus and receiving the sequence of bytes into a second buffer delayed one clock cycle from the first buffer. The method further includes providing the sequence of bytes from the first buffer to an output buffer, counting clock cycles of data as the data is received into the first and second buffers, upon reaching a predetermined count, inserting a dead cycle into the output buffer, and after inserting the dead cycle providing the sequence of bytes from the second buffer instead of the first buffer to the output buffer.

摘要翻译： 使用块对准器描述了去偏死死循环的方法和装置。 在一个示例中，一种方法包括从多通道外围设备总线的每个通道接收到第一缓冲器中的字节序列，并将字节序列接收到从第一缓冲器延迟一个时钟周期的第二缓冲器。 该方法还包括从第一缓冲器向输出缓冲器提供字节序列，当达到预定的计数，将死循环插入到输出缓冲器中时，对数据的时钟周期进行计数，当数据被接收到第一和第二缓冲器中时， 并且在将来自第二缓冲器而不是第一缓冲器的字节序列插入到输出缓冲器之后插入死循环。

公开(公告)号：US09372501B2

公开(公告)日：2016-06-21

申请号：US13977500

申请日：2011-12-22

申请人： Shrinivas Venkatraman

发明人： Shrinivas Venkatraman

IPC分类号： G06F1/10 ,  G06K5/04 ,  G06F13/00

CPC分类号： G06F1/10 ,  G06F13/00 ,  G06F13/4221 ,  G06K5/04

摘要： A method and apparatus to deskew dead cycles is described using a block aligner. In one example a method includes receiving a sequence of bytes into a first buffer from each lane of a multiple lane peripheral device bus and receiving the sequence of bytes into a second buffer delayed one clock cycle from the first buffer. The method further includes providing the sequence of bytes from the first buffer to an output buffer, counting clock cycles of data as the data is received into the first and second buffers, upon reaching a predetermined count, inserting a dead cycle into the output buffer, and after inserting the dead cycle providing the sequence of bytes from the second buffer instead of the first buffer to the output buffer.

摘要翻译： 使用块对准器描述了去偏死死循环的方法和装置。 在一个示例中，一种方法包括从多通道外围设备总线的每个通道接收到第一缓冲器中的字节序列，并将字节序列接收到从第一缓冲器延迟一个时钟周期的第二缓冲器。 该方法还包括从第一缓冲器向输出缓冲器提供字节序列，当达到预定计数，将死循环插入到输出缓冲器中时，数据被接收到第一和第二缓冲器中时，计数数据的时钟周期， 并且在将来自第二缓冲器而不是第一缓冲器的字节序列插入到输出缓冲器之后插入死循环。

公开(公告)号：US20140237301A1

公开(公告)日：2014-08-21

申请号：US13767881

申请日：2013-02-15

申请人： Ivan Herrera Mejia ,  Manuel A. Aguilar Arreola ,  Shrinivas Venkatraman ,  Andrea R. Vavra ,  Pavel Konev

发明人： Ivan Herrera Mejia ,  Manuel A. Aguilar Arreola ,  Shrinivas Venkatraman ,  Andrea R. Vavra ,  Pavel Konev

IPC分类号： G06F11/30

CPC分类号： G06F13/4282 ,  G06F9/4411 ,  G06F13/385 ,  G06F13/4072 ,  G06F2213/0026

摘要： Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.

摘要翻译： 描述了利用预设评估来提高高速串行互连中的输入/输出性能的方法和装置。 在一些实施例中，在多个均衡值处评估链路的性能，并且基于为多个均衡值中的每一个确定的多个边缘值的比较来为链路选择多个均衡值中的一个 价值观。 还要求和/或公开其它实施例。