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    INTERNAL VIRTUAL NETWORK IDENTIFIER AND INTERNAL POLICY IDENTIFIER
    1.
    发明申请
    INTERNAL VIRTUAL NETWORK IDENTIFIER AND INTERNAL POLICY IDENTIFIER 审中-公开
    内部虚拟网络标识符和内部策略标识符

    公开(公告)号：US20110299533A1

    公开(公告)日：2011-12-08

    申请号：US13050102

    申请日：2011-03-17

    申请人： Shunjia Yu ,  Anoop Ghanwani ,  Phanidhar Koganti ,  Mythilikanth Raman ,  Rajiv Krishnamurthy ,  John Michael Terry ,  Wing Cheung ,  Joseph Juh-En Cheng ,  Surya P. Varanasi

    发明人： Shunjia Yu ,  Anoop Ghanwani ,  Phanidhar Koganti ,  Mythilikanth Raman ,  Rajiv Krishnamurthy ,  John Michael Terry ,  Wing Cheung ,  Joseph Juh-En Cheng ,  Surya P. Varanasi

    IPC分类号： H04L12/56

    CPC分类号： H04L12/4604 ,  H04L12/4625

    摘要： Systems and techniques for processing and forwarding packets are described. Some embodiments provide a system (e.g., a switch) which determines an internal virtual network identifier and/or an internal policy identifier for a packet based on a port on which the packet was received and/or one or more fields in the packet. The system can then process and forward the packet based on the internal virtual network identifier and/or internal policy identifier. In some embodiments, the system encapsulates the packet in a TRILL (Transparent Interconnection of Lots of Links) packet by adding a TRILL header to the packet. In some embodiments, the scope of an internal virtual network identifier and/or an internal policy identifier may not extend beyond a switch or a module within a switch.

    摘要翻译： 描述了处理和转发数据包的系统和技术。 一些实施例提供了一种系统（例如交换机），其基于接收到分组的端口和/或分组中的一个或多个字段来确定分组的内部虚拟网络标识符和/或内部策略标识符。 然后系统可以基于内部虚拟网络标识符和/或内部策略标识符处理和转发数据包。 在一些实施例中，通过向分组添加TRILL报头，系统将分组封装在TRILL（多个链路的透明互连）分组中。 在一些实施例中，内部虚拟网络标识符和/或内部策略标识符的范围可能不会超出交换机内的交换机或模块。

    PRESERVING QUALITY OF SERVICE ACROSS TRILL NETWORKS
    2.
    发明申请
    PRESERVING QUALITY OF SERVICE ACROSS TRILL NETWORKS 审中-公开
    保持网络服务质量

    公开(公告)号：US20110299414A1

    公开(公告)日：2011-12-08

    申请号：US13048817

    申请日：2011-03-15

    申请人： Shunjia Yu ,  Anoop Ghanwani ,  Phanidhar Koganti ,  John Michael Terry ,  Wing Cheung ,  Joseph Juh-En Cheng ,  Surya P. Varanasi

    发明人： Shunjia Yu ,  Anoop Ghanwani ,  Phanidhar Koganti ,  John Michael Terry ,  Wing Cheung ,  Joseph Juh-En Cheng ,  Surya P. Varanasi

    IPC分类号： H04L12/26

    CPC分类号： H04L47/2491 ,  H04L12/4641 ,  H04L45/00 ,  H04L45/66

    摘要： Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.

    摘要翻译： 描述用于处理和/或转发分组的系统和技术。 入口交换机可以使用QoS映射机制来将从客户端接收的分组中的第一组服务质量（QoS）比特映射到第二组QoS比特，以用于多个链路（TRILL）分组的透明互连 它封装了数据包。 第一组QoS位可以与第二组QoS位不同。 TRILL分组可以基于第二组QoS比特在网络中被处理和/或转发。 在出口交换机上，可以对TRILL数据包进行解封装，将原始QoS位（或不同于原始QoS位的QoS位）的原始数据包转发到客户的网络。 以这种方式，本发明的一些实施例可以保持跨TRILL网络的QoS比特。

    Architecture for decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements
    6.
    发明授权
    Architecture for decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements 失效
    用于解码MPEG兼容视频比特流的架构，满足2帧和letterboxing要求

    公开(公告)号：US06289053B1

    公开(公告)日：2001-09-11

    申请号：US08904084

    申请日：1997-07-31

    申请人： Surya P. Varanasi ,  Satish Soman

    发明人： Surya P. Varanasi ,  Satish Soman

    IPC分类号： A04N732

    CPC分类号： H04N19/42 ,  H04N19/61

    摘要： A system and method for performing motion compensation in an MPEG video decoder. The system comprises a horizontal half pixel compensation arrangement including multiple adders and multiplexers which perform horizontal half pixel compensation using an addition function, a division function, and a modulo function on pixel data. The system also includes a register bank which provides the ability to store an array of reference data when vertical half pixel compensation is required. The system also includes a verical half pixel compensation arrangement, which also includes multiple adders and multiplexers which perform vertical half pixel compensation using an addition function, a division function, and a modulo function on pixel data. Reference data and odd pixel data is transferred into and within the system in a predetermined arrangement. Reference and odd pel data may comprise either luma or chroma data. Different picture types, prediction types, and pixel compensation requirements yield different data fetching schemes for luma and chroma data, and different reference motion vector data causes different luma and chroma transference to the motion compensation unit. The system also performs reference data averaging between various frames using a B-picture compensation unit, which operates when B-pictures with backward and forward motion vectors or P-pictures with dual-prime prediction occur.

    摘要翻译： 一种用于在MPEG视频解码器中执行运动补偿的系统和方法。 该系统包括水平半像素补偿装置，其包括使用加法函数，除法函数和像素数据上的模函数执行水平半像素补偿的多个加法器和多路复用器。 该系统还包括一个寄存器组，其在需要垂直半像素补偿时提供存储参考数据阵列的能力。 该系统还包括一个虚拟的半像素补偿装置，它还包括使用加法函数，除法函数和像素数据上的模函数执行垂直半像素补偿的多个加法器和多路复用器。 参考数据和奇数像素数据以预定的布置传送到系统内部和系统内。 参考和奇数像素数据可以包括亮度或色度数据。 不同的图像类型，预测类型和像素补偿要求产生亮度和色度数据的不同数据提取方案，不同的参考运动矢量数据导致运动补偿单元的不同亮度和色度传递。 该系统还使用B图像补偿单元在各帧之间进行平均化的参考数据，该B图像补偿单元在具有反向和向前运动矢量的B图像或双重预测的P图像发生时操作。

    Host bus adapter with multiple hosts
    7.
    发明授权
    Host bus adapter with multiple hosts 有权
    具有多个主机的主机总线适配器

    公开(公告)号：US07669000B2

    公开(公告)日：2010-02-23

    申请号：US11877116

    申请日：2007-10-23

    申请人： Prateek Sharma ,  Tony Sonthe Nguyen ,  Gregory S. Walter ,  Surya P. Varanasi

    发明人： Prateek Sharma ,  Tony Sonthe Nguyen ,  Gregory S. Walter ,  Surya P. Varanasi

    IPC分类号： G06F13/36

    CPC分类号： G06F13/385

    摘要： A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host.

    摘要翻译： 可以将多主机主机总线适配器（HBA）连接到多个主机设备，以允许多个主机设备在SAN结构上进行通信。 更具体地说，多主机HBA为多个SAN主机提供了一个接口，而不需要每个主机上的HBA，从而无需在每个SAN主机上使用板载HBA。 多主机HBA与使用PCI-Express（或类似协议）连接的每个SAN主机中的内存进行接口，并使用光纤通道端口与SAN结构上的其他设备进行通信。 多主机HBA通过从连接的主机接收命令进行通信，将命令转发到多主机HBA中的处理器，并将命令发送到SAN上的设备。 当多主机HBA从SAN上的设备收到响应时，多主机HBA将响应与进程相关联，并将响应发送给主机。

    System and method for low delay mode operation video decoding
    8.
    发明授权
    System and method for low delay mode operation video decoding 失效
    低延迟模式操作视频解码的系统和方法

    公开(公告)号：US06266091B1

    公开(公告)日：2001-07-24

    申请号：US08920511

    申请日：1997-08-29

    申请人： Angshuman Saha ,  Satish Soman ,  Surya P. Varanasi

    发明人： Angshuman Saha ,  Satish Soman ,  Surya P. Varanasi

    IPC分类号： H04N736

    CPC分类号： H04N19/42 ,  H04N19/61

    摘要： A system and method for low delay mode operation video decoding embodied in a prefetch buffer and an mbcore including an mbcore pipeline. The mbcore is adapted to check a status of the prefetch buffer at predetermined times and to implement a low delay mode to delay the mbcore pipeline when a data level of the prefetch buffer goes below a threshold at the predetermined times. The mbcore is adapted to ensure that there is a sufficient quantity of data in the prefetch buffer for a particular operation and, in a preferred embodiment, is adapted to check the status of the prefetch buffer at a start of a slice, at a beginning of dct decoding of each coded block. The prefetch buffer and the mbcore operate asynchronously, with the mbcore being adapted to prevent a symbol from splitting between the prefetch buffer and the mbcore.

    摘要翻译： 用于低延迟模式操作的系统和方法，其包含在预取缓冲器和包括mbcore管线的mbcore中。 mbcore适于在预定时间检查预取缓冲器的状态，并且当预取缓冲器的数据电平在预定时间内低于阈值时，实现低延迟模式以延迟mbcore流水线。 mbcore适于确保在特定操作的预取缓冲器中存在足够数量的数据，并且在优选实施例中，适于在片的开始处检查预取缓冲器的状态， 每个编码块的dct解码。 预取缓冲区和mbcore异步运行，mbcore适用于防止符号在预取缓冲区和mbcore之间分裂。

    Video bitstream symbol extractor for use in decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements
    9.
    发明授权
    Video bitstream symbol extractor for use in decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements 失效
    视频位流符号提取器，用于解码满足2帧和信箱要求的MPEG兼容视频比特流

    公开(公告)号：US6101221A

    公开(公告)日：2000-08-08

    申请号：US904088

    申请日：1997-07-31

    申请人： Surya P. Varanasi ,  Satish Soman

    发明人： Surya P. Varanasi ,  Satish Soman

    IPC分类号： H04N7/26 ,  H04N7/36 ,  H04N7/50

    CPC分类号： H04N19/42 ,  H04N19/44 ,  H04N19/61 ,  H04N19/91

    摘要： A system and method for decoding fixed length data words comprising variable length objects is disclosed having the ability to decode a variable length DCT in every clock cycle. The system includes multiple floating point registers, preferably two, for holding the fixed length data words, and a tracking arrangement, including a summation block and a total used bits register, where the summation block sums bits used for each variable length object with the contents of the total bits used register to form the total number of used bits. The total used bits are fed back and summed within the total used bits register.The system also has a rotating shift register, which is a circular buffer, and a multiplexer arrangement which transfers variable length objects from the floating point registers to the rotating shift register. The tracking arrangement counts the bits used in transferring variable length objects to the rotating shift register. The floating point registers access additional fixed length data words when emptied. The multiplexer arrangement includes one multiplexer is associated with each floating point register and is capable of receiving new data. Each multiplexer transfers data from its associated floating point register to the rotating shift register. The transfer of variable length objects may require data contained in more than one floating point register and transfer using more than one multiplexer. The system also includes a resultant floating point register, where the rotating shift register shifts complete data words data thereto.

    摘要翻译： 公开了一种用于解码包括可变长度对象的固定长度数据字的系统和方法，其具有在每个时钟周期中解码可变长度DCT的能力。 该系统包括多个用于保持固定长度数据字的浮点寄存器，以及包括求和块和总使用比特寄存器的跟踪装置，其中求和块将用于每个可变长度对象的比特与内容 使用的总位数寄存器形成已使用位的总数。 总使用的位被反馈并在总使用位寄存器内相加。 该系统还具有循环移位寄存器，它是一个循环缓冲器，以及一个多路复用器装置，它将可变长度的对象从浮点寄存器传送到旋转移位寄存器。 跟踪装置将用于将可变长度对象传送到旋转移位寄存器的位进行计数。 浮点寄存器在清空时访问其他固定长度的数据字。 多路复用器装置包括一个多路复用器与每个浮点寄存器相关联并且能够接收新的数据。 每个复用器将数据从相关联的浮点寄存器传送到旋转移位寄存器。 可变长度对象的传输可能需要包含在多个浮点寄存器中的数据，并使用多个多路复用器进行传输。 该系统还包括结果浮点寄存器，其中旋转移位寄存器将完整的数据字数据移位到其上。

    HOST BUS ADAPTER WITH MULTIPLE HOSTS
    10.
    发明申请
    HOST BUS ADAPTER WITH MULTIPLE HOSTS 有权
    主机总线适配器多个主机

    公开(公告)号：US20090106470A1

    公开(公告)日：2009-04-23

    申请号：US11877116

    申请日：2007-10-23

    申请人： Prateek Sharma ,  Tony Sonthe Nguyen ,  Gregory S. Walter ,  Surya P. Varanasi

    发明人： Prateek Sharma ,  Tony Sonthe Nguyen ,  Gregory S. Walter ,  Surya P. Varanasi

    IPC分类号： G06F13/36 ,  G06F13/14

    CPC分类号： G06F13/385

    摘要： A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host.

    摘要翻译： 可以将多主机主机总线适配器（HBA）连接到多个主机设备，以允许多个主机设备在SAN结构上进行通信。 更具体地说，多主机HBA为多个SAN主机提供了一个接口，而不需要每个主机上的HBA，从而无需在每个SAN主机上使用板载HBA。 多主机HBA与使用PCI-Express（或类似协议）连接的每个SAN主机中的内存进行接口，并使用光纤通道端口与SAN结构上的其他设备进行通信。 多主机HBA通过从连接的主机接收命令进行通信，将命令转发到多主机HBA中的处理器，并将命令发送到SAN上的设备。 当多主机HBA从SAN上的设备收到响应时，多主机HBA将响应与进程相关联，并将响应发送给主机。