利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

80 条记录 (耗时 0.029 秒)

    Shift register and display device using same
    1.
    发明授权
    Shift register and display device using same 有权
    移位寄存器和显示设备使用相同

    公开(公告)号：US07733321B2

    公开(公告)日：2010-06-08

    申请号：US11543219

    申请日：2006-10-05

    申请人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

    发明人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

    IPC分类号： G09G3/36

    CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

    摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

    摘要翻译： 移位寄存器包括多级触发器。 作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。 在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入 信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。 通过这种布置，可以防止由于不能重置触发器而引起的电路故障。

    Shift register and display device using same
    3.
    发明申请
    Shift register and display device using same 有权
    移位寄存器和显示设备使用相同

    公开(公告)号：US20070024567A1

    公开(公告)日：2007-02-01

    申请号：US11543218

    申请日：2006-10-05

    申请人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

    发明人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

    IPC分类号： G09G3/36

    CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

    摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

    摘要翻译： 移位寄存器包括多级触发器。 作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。 在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入 信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。 通过这种布置，可以防止由于不能重置触发器而引起的电路故障。

    Level shifter circuit and display device provided therewith
    6.
    发明授权
    Level shifter circuit and display device provided therewith 有权
    电平移位电路和显示装置

    公开(公告)号：US08248348B2

    公开(公告)日：2012-08-21

    申请号：US11812461

    申请日：2007-06-19

    申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

    发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

    IPC分类号： H03K19/0175 ,  H03L5/00 ,  G09G5/00 ,  G09G3/28 ,  G09G3/36

    CPC分类号： G09G3/3611 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018521

    摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

    摘要翻译： 电平移位电路包括第一和第二电平移位器，其分别输出通过电平移位高电平周期不重叠的两种输入时钟信号产生的第一和第二输出信号。 电平移位电路还包括控制晶体管和控制线，其一起在第一输出信号为高电平时防止馈通电流流入第二电平移位器，并且当第二电平移位器第二输出信号为高电平时，防止馈通电流流入第一电平移位器 输出信号是高电平，以便暂停第一和第二电平移位器的电平移位操作。 利用电平移位电路，可以消除在时钟信号的非有效周期中的特定时间段内的功率消耗，其中一个时钟信号的特定时间周期是另一个时钟信号的有效周期。

    Scanning direction control circuit and display device
    7.
    发明授权
    Scanning direction control circuit and display device 有权
    扫描方向控制电路和显示装置

    公开(公告)号：US07289097B2

    公开(公告)日：2007-10-30

    申请号：US10702077

    申请日：2003-11-06

    申请人： Seijirou Gyouten ,  Sachio Tsujino ,  Hajime Washio ,  Eiji Matsuda ,  Keiichi Ina ,  Yuhichiroh Murakami ,  Shunsuke Hayashi ,  Mamoru Onda

    发明人： Seijirou Gyouten ,  Sachio Tsujino ,  Hajime Washio ,  Eiji Matsuda ,  Keiichi Ina ,  Yuhichiroh Murakami ,  Shunsuke Hayashi ,  Mamoru Onda

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0283 ,  G09G2310/0289 ,  G11C19/00 ,  G11C19/28

    摘要： The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.

    摘要翻译： 本发明公开了一种扫描方向控制电路，其包括双向移位寄存器，其中根据切换信号L / R切换移位方向，当切换信号L / R在比驱动电压低的振幅时由电平移位器升压。 扫描方向控制电路包括电平移位器和双向移位寄存器之间的锁存电路，并且控制电路使得锁存电路在构成双向移位寄存器的触发器的移位操作之后响应于输出而完成锁存操作 触发器的信号。 控制电路在锁存定时之前，之后和之后的时段中使电平移位器进入有效状态，并且在剩余时间段内使电平移位器进入非活动状态。 利用这种布置，可以在低功耗的情况下以预定的时序提供开关信号L / R，而不管其外部输入定时。

    Level shifter circuit and display device provided therewith
    9.
    发明授权
    Level shifter circuit and display device provided therewith 有权
    电平移位电路和显示装置

    公开(公告)号：US07248243B2

    公开(公告)日：2007-07-24

    申请号：US10438886

    申请日：2003-05-16

    申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Shunsuke Hayashi ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino

    发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Shunsuke Hayashi ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino

    IPC分类号： H03K19/0175 ,  H03L5/00 ,  G09G3/28 ,  G09G3/36 ,  G09G5/00

    CPC分类号： G09G3/3611 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018521

    摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

    摘要翻译： 电平移位电路包括第一和第二电平移位器，其分别输出通过电平移位高电平周期不重叠的两种输入时钟信号产生的第一和第二输出信号。 电平移位电路还包括控制晶体管和控制线，其一起在第一输出信号为高电平时防止馈通电流流入第二电平移位器，并且当第二电平移位器第二输出信号为高电平时，防止馈通电流流入第一电平移位器 输出信号是高电平，以便暂停第一和第二电平移位器的电平移位操作。 利用电平移位电路，可以消除在时钟信号的非有效周期中的特定时间段内的功率消耗，其中一个时钟信号的特定时间周期是另一个时钟信号的有效周期。

    Shift register and display device using the same
    10.
    发明授权
    Shift register and display device using the same 有权
    移位寄存器和显示设备使用相同

    公开(公告)号：US07659877B2

    公开(公告)日：2010-02-09

    申请号：US10887308

    申请日：2004-07-09

    申请人： Yuhichiroh Murakami ,  Hajime Washio ,  Sachio Tsujino ,  Seijirou Gyouten ,  Eiji Matsuda

    发明人： Yuhichiroh Murakami ,  Hajime Washio ,  Sachio Tsujino ,  Seijirou Gyouten ,  Eiji Matsuda

    IPC分类号： G09G3/36

    CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2330/021

    摘要： A shift register includes control circuits CNi (i=1 through n) corresponding to respective blocks, and a level shifter LSi+1 of the next stage is controlled by one of the outputs of the shift register and one of the outputs of flip-flops Fi. With this, a level shifter of the present stage operates only for a period minimum for outputting the shift output from the present block, so that the power consumption is reduced, Furthermore, it is possible to cause the outputs SL1 through SLn not to overlap each other.

    摘要翻译： 移位寄存器包括对应于各个块的控制电路CNi（i = 1至n），并且下一级的电平移位器LSi + 1由移位寄存器的输出之一和触发器的输出之一 Fi。 由此，本阶段的电平移位器仅对于从当前块输出移位输出的期间最小化，从而能够降低功耗。此外，可以使输出SL1〜SLn不与各块重叠 其他。