公开(公告)号：US07311852B2

公开(公告)日：2007-12-25

申请号：US09820695

申请日：2001-03-30

申请人： Si Yi Li ,  Helen H. Zhu ,  S. M. Reza Sadjadi ,  James V. Tietz ,  Bryan A. Helmer

发明人： Si Yi Li ,  Helen H. Zhu ,  S. M. Reza Sadjadi ,  James V. Tietz ,  Bryan A. Helmer

IPC分类号： H01L21/3065

CPC分类号： H01L21/7681 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76807

摘要： A semiconductor manufacturing process wherein a low-k dielectric layer is plasma etched with selectivity to an overlying mask layer. The etchant gas can be oxygen-free and include a fluorocarbon reactant, a nitrogen reactant and an optional carrier gas, the fluorocarbon reactant and nitrogen reactant being supplied to a chamber of a plasma etch reactor at flow rates such that the fluorocarbon reactant flow rate is less than the nitrogen reactant flow rate. The etch rate of the low-k dielectric layer can be at least 5 times higher than that of a silicon dioxide, silicon nitride, silicon oxynitride or silicon carbide mask layer. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.

摘要翻译： 一种半导体制造工艺，其中低k电介质层被等离子体蚀刻，对上覆掩模层具有选择性。 蚀刻剂气体可以是无氧的并且包括氟碳反应物，氮反应物和任选的载气，所述碳氟反应物和氮反应物以流速供给到等离子体蚀刻反应器的室，使得碳氟化合物反应物流速为 小于氮气反应物流量。 低k电介质层的蚀刻速率可以比二氧化硅，氮化硅，氮氧化硅或碳化硅掩模层的蚀刻速率高至少5倍。 该方法对于在形成结构如镶嵌结构中蚀刻0.25微米和较小的接触或通孔开口是有用的。

公开(公告)号：US06540885B1

公开(公告)日：2003-04-01

申请号：US09821427

申请日：2001-03-28

申请人： Douglas Keil ,  Eric Wagganer ,  Bryan A. Helmer

发明人： Douglas Keil ,  Eric Wagganer ,  Bryan A. Helmer

IPC分类号： C23C1400

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/76807

摘要： Methods for etching a trench into a dielectric layer are provided. One exemplary method controls an ion-to-neutral flux ratio during etching so as to achieve a neutral limited regime in an ion assisted etch mechanism where the neutral limited regime causes bottom rounding. The method includes modulating physical sputtering causing microtrenching to offset the bottom rounding so as to produce a substantially flat bottom trench profile. Some notable advantages of the discussed methods of etching a trench into a dielectric layer includes the ability to eliminate the intermediate etch stop layer. Elimination of the etch stop layer will decrease fabrication cost and process time. Additionally, the elimination of the intermediate stop layer will improve device performance.

摘要翻译： 提供了将沟槽刻蚀成电介质层的方法。 一种示例性方法控制蚀刻期间的离子 - 中性流量比，以便在离子辅助蚀刻机制中实现中性限制的状态，其中中性限制状态导致底部四舍五入。 该方法包括调制物理溅射，导致微切削以抵消底部四舍五入，以便产生基本平坦的底部沟槽轮廓。 所讨论的将沟槽蚀刻到电介质层中的方法的一些显着的优点包括消除中间蚀刻停止层的能力。 消除蚀刻停止层将降低制造成本和处理时间。 此外，中间停止层的消除将提高装置性能。