公开(公告)号：US20140050243A1

公开(公告)日：2014-02-20

申请号：US13995689

申请日：2011-12-22

申请人： Siddharth Jain ,  John Bowers ,  Matthew Sysak ,  John Heck ,  Ran Feldesh ,  Richard Jones ,  Yoel Shetrit ,  Michael Geva

发明人： Siddharth Jain ,  John Bowers ,  Matthew Sysak ,  John Heck ,  Ran Feldesh ,  Richard Jones ,  Yoel Shetrit ,  Michael Geva

IPC分类号： H01L23/00

CPC分类号： H01L24/45 ,  H01L21/28575 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/8258 ,  H01L27/1203 ,  H01L29/20 ,  H01L29/452 ,  H01L2224/45 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/12042 ,  H01S5/021 ,  H01S5/0425 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/43

摘要： A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.

摘要翻译： 半导体冶金学包括对n型材料和p型材料提供低接触电阻的锗和钯的比例。 冶金允许不包括金的接触，并且与大规模生产CMOS技术兼容。 锗和钯的比例可以通过堆叠材料的层并退火叠层来实现，或者同时将锗和钯沉积在要制造接触的材料上。

公开(公告)号：US09252118B2

公开(公告)日：2016-02-02

申请号：US13995689

申请日：2011-12-22

申请人： Siddharth Jain ,  John Bowers ,  Matthew Sysak ,  John Heck ,  Ran Feldesh ,  Richard Jones ,  Yoel Shetrit ,  Michael Geva

发明人： Siddharth Jain ,  John Bowers ,  Matthew Sysak ,  John Heck ,  Ran Feldesh ,  Richard Jones ,  Yoel Shetrit ,  Michael Geva

IPC分类号： H01S5/042 ,  H01L23/00 ,  H01L21/8238 ,  H01L21/8258 ,  H01L21/285 ,  H01L29/45 ,  H01L27/12 ,  H01L29/20 ,  H01S5/02

CPC分类号： H01L24/45 ,  H01L21/28575 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/8258 ,  H01L27/1203 ,  H01L29/20 ,  H01L29/452 ,  H01L2224/45 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/12042 ,  H01S5/021 ,  H01S5/0425 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/43

摘要： A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.

摘要翻译： 半导体冶金学包括对n型材料和p型材料提供低接触电阻的锗和钯的比例。 冶金允许不包括金的接触，并且与大规模生产CMOS技术兼容。 锗和钯的比例可以通过堆叠材料的层并退火叠层来实现，或者同时将锗和钯沉积在要制造接触的材料上。

公开(公告)号：US20140307997A1

公开(公告)日：2014-10-16

申请号：US13976913

申请日：2011-12-20

申请人： Hanan Bar ,  John Heck ,  Avi Feshali ,  Ran Feldesh

发明人： Hanan Bar ,  John Heck ,  Avi Feshali ,  Ran Feldesh

IPC分类号： G02B6/122 ,  H01L21/8252 ,  H01L29/205 ,  G02B6/13

CPC分类号： G02B6/1225 ,  G02B6/12004 ,  G02B6/13 ,  G02B2006/12061 ,  H01L21/28575 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/205

摘要： Photonic passivation layers, III-V semiconductor die with offcut edges, and NiGe contact metallization for silicon-based photonic integrated circuits (PICs). In embodiments, a non-sacrificial passivation layer is formed on a silicon photonic element, such as a waveguide for protection of the waveguide surfaces. In embodiments, a III-V semiconductor film is transferred from a III-V growth substrate that is singulated along streets that are misaligned from cleave planes to avoid crystallographic etch artifacts in a layer transfer process. In embodiments, a NiGe contact metallization is employed for both p-type and n-type contacts on a device formed in the transferred III-V semiconductor layer to provide low specific contact resistance and compatibility with MOS processes.

摘要翻译： 光子钝化层，具有切割边缘的III-V半导体管芯和用于硅基光子集成电路（PIC）的NiGe接触金属化。 在实施例中，在硅光子元件（例如用于保护波导表面的波导）上形成非牺牲钝化层。 在实施例中，III-V半导体膜从沿切割面不对准的街道上被切割的III-V生长衬底转移，以避免层转移过程中的晶体学蚀刻伪影。 在实施例中，NiGe接触金属化用于形成在转移的III-V半导体层中的器件上的p型和n型触点，以提供低的比接触电阻和与MOS工艺的兼容性。