公开(公告)号：US20140050243A1

公开(公告)日：2014-02-20

申请号：US13995689

申请日：2011-12-22

Applicant: Siddharth Jain ,  John Bowers ,  Matthew Sysak ,  John Heck ,  Ran Feldesh ,  Richard Jones ,  Yoel Shetrit ,  Michael Geva

Inventor： Siddharth Jain ,  John Bowers ,  Matthew Sysak ,  John Heck ,  Ran Feldesh ,  Richard Jones ,  Yoel Shetrit ,  Michael Geva

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L21/28575 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/8258 ,  H01L27/1203 ,  H01L29/20 ,  H01L29/452 ,  H01L2224/45 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/12042 ,  H01S5/021 ,  H01S5/0425 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/43

Abstract: A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.

Abstract translation: 半导体冶金学包括对n型材料和p型材料提供低接触电阻的锗和钯的比例。 冶金允许不包括金的接触，并且与大规模生产CMOS技术兼容。 锗和钯的比例可以通过堆叠材料的层并退火叠层来实现，或者同时将锗和钯沉积在要制造接触的材料上。

公开(公告)号：US4755671A

公开(公告)日：1988-07-05

申请号：US824828

申请日：1986-01-31

Applicant: Lazar Friedland ,  Michael Geva ,  Jay Hirshfield

Inventor： Lazar Friedland ,  Michael Geva ,  Jay Hirshfield

IPC: B01D59/44 ,  H01J49/30

CPC classification number: B01D59/44

Abstract: A method and apparatus for separating plural isotopes of a chemical substance is disclosed. The apparatus comprises a first magnetic field generating device for generating a uniform axial first magnetic field and a second magnetic field generating device such as a wiggler for generating a non-uniform, twisted, second magnetic field. An ion source provides a stream of ions of isotopes to be separated, the stream passing through the first and second magnetic fields. Ions of different charge-to-mass ratio will follow different trajectories or paths through the magnetic fields. A collector is positioned with respect to the second magnetic field generating device such that only the ions of isotopes to be collected strike the collector means and are collected thereon. The method includes generating the first and second magnetic fields and passing a stream of ions to be separated through the first and second magnetic field, whereby ions of different charge-to-mass ratio travel along different predetermined paths or trajectories. The ions of the isotope following at least one of the predetermined paths are then collected.

Abstract translation: 公开了一种用于分离化学物质的多个同位素的方法和装置。 该装置包括用于产生均匀的轴向第一磁场的第一磁场产生装置和用于产生不均匀的扭转的第二磁场的诸如摆动器的第二磁场产生装置。 离子源提供待分离的同位素离子流，该流通过第一和第二磁场。 不同电荷质量比的离子将遵循通过磁场的不同轨迹或路径。 收集器相对于第二磁场产生装置定位，使得只有待收集的同位素的离子撞击收集器装置并在其上收集。 该方法包括产生第一和第二磁场并使待分离的离子流通过第一和第二磁场，由此不同电荷质量比的离子沿着不同的预定路径或轨迹行进。 然后收集遵循至少一个预定路径的同位素离子。

公开(公告)号：US06706542B1

公开(公告)日：2004-03-16

申请号：US09645913

申请日：2000-08-25

Applicant: Michael Geva ,  Yuliya Anatolyevna Akulova ,  Abdallah Ougazzaden

Inventor： Michael Geva ,  Yuliya Anatolyevna Akulova ,  Abdallah Ougazzaden

IPC: H01L2100

CPC classification number: H01S5/227 ,  H01L21/2205 ,  H01L33/02 ,  H01L33/305 ,  H01S5/2209 ,  H01S5/221 ,  H01S5/2224 ,  H01S5/2226 ,  H01S5/2227 ,  H01S5/2272 ,  H01S5/3072

Abstract: The present invention relates to a multi-layer dopant barrier and its method of fabrication for use in semiconductor structures. In an illustrative embodiment, the multi-layer dopant barrier is disposed between a first doped layer and a second doped layer. The multi-layer dopant barrier further includes a first dopant blocking layer adjacent the first doped layer and a second dopant blocking layer adjacent the second doped layer. A technique for fabricating the multi layer dopant barrier is disclosed. A first dopant blocking layer is formed at a first temperature, and a second dopant blocking layer is formed at a second temperature over the first barrier layer.

Abstract translation: 本发明涉及一种用于半导体结构的多层掺杂剂阻挡层及其制造方法。 在说明性实施例中，多层掺杂剂阻挡层设置在第一掺杂层和第二掺杂层之间。 多层掺杂剂阻挡层还包括与第一掺杂层相邻的第一掺杂剂阻挡层和与第二掺杂层相邻的第二掺杂剂阻挡层。 公开了一种用于制造多层掺杂剂阻挡层的技术。 在第一温度下形成第一掺杂剂阻挡层，并且在第一阻挡层上的第二温度下形成第二掺杂剂阻挡层。

公开(公告)号：US09252118B2

公开(公告)日：2016-02-02

申请号：US13995689

申请日：2011-12-22

Applicant: Siddharth Jain ,  John Bowers ,  Matthew Sysak ,  John Heck ,  Ran Feldesh ,  Richard Jones ,  Yoel Shetrit ,  Michael Geva

Inventor： Siddharth Jain ,  John Bowers ,  Matthew Sysak ,  John Heck ,  Ran Feldesh ,  Richard Jones ,  Yoel Shetrit ,  Michael Geva

IPC: H01S5/042 ,  H01L23/00 ,  H01L21/8238 ,  H01L21/8258 ,  H01L21/285 ,  H01L29/45 ,  H01L27/12 ,  H01L29/20 ,  H01S5/02

CPC classification number: H01L24/45 ,  H01L21/28575 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/8258 ,  H01L27/1203 ,  H01L29/20 ,  H01L29/452 ,  H01L2224/45 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/12042 ,  H01S5/021 ,  H01S5/0425 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/43

Abstract: A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.

Abstract translation: 半导体冶金学包括对n型材料和p型材料提供低接触电阻的锗和钯的比例。 冶金允许不包括金的接触，并且与大规模生产CMOS技术兼容。 锗和钯的比例可以通过堆叠材料的层并退火叠层来实现，或者同时将锗和钯沉积在要制造接触的材料上。

公开(公告)号：US06520348B1

公开(公告)日：2003-02-18

申请号：US09542622

申请日：2000-04-04

Applicant: Dutt V. Bulusu ,  Robert L. Mcanally ,  Michael Geva ,  Gustav E. Derkits ,  Robert A. Resta

Inventor： Dutt V. Bulusu ,  Robert L. Mcanally ,  Michael Geva ,  Gustav E. Derkits ,  Robert A. Resta

IPC: A47G1908

CPC classification number: H01L21/67313 ,  Y10S414/138

Abstract: An apparatus and method for diffusion annealing impurities onto a plurality of wafers is described. A hollow wafer holder includes a plurality of first and second slots. The first slots are sized and shaped to receive a pair of wafers. The first slots are angled relative to a longitudinal axis of the wafer holder. The wafer holder is positioned at a first location within an ampoule, with a diffusion source being positioned at a second location within the ampoule. The ampoule is sealed and placed within or near a heat source. The heat source alters the physical state of the diffusion source to allow the entrained impurities to diffuse throughout the ampoule. The inclination of the first slots allows a sufficient clearance between the wafers and the ampoule to allow impurities within a gaseous diffusion source to extend throughout the ampoule. The presence of the second slots allows a more uniform diffusion of the impurities to the wafers.

Abstract translation: 描述了将杂质扩散到多个晶片上的装置和方法。 中空晶片保持器包括多个第一和第二槽。 第一槽的尺寸和形状适于接收一对晶片。 第一狭槽相对于晶片保持器的纵向轴线成角度。 晶片保持器位于安瓿内的第一位置处，扩散源位于安瓿内的第二位置。 将安瓿密封并置于热源内或附近。 热源改变扩散源的物理状态，以允许夹带的杂质扩散到整个安瓿中。 第一槽的倾斜允许晶片和安瓿之间的足够的间隙允许气体扩散源中的杂质延伸贯穿整个安瓿。 第二槽的存在允许杂质更均匀地扩散到晶片。

公开(公告)号：US06819695B1

公开(公告)日：2004-11-16

申请号：US09540471

申请日：2000-03-31

Applicant: Yuliya Anatolyevna Akulova ,  Michael Geva ,  Abdallah Ougazzaden

Inventor： Yuliya Anatolyevna Akulova ,  Michael Geva ,  Abdallah Ougazzaden

IPC: H01S500

CPC classification number: H01S5/227 ,  H01L21/2205 ,  H01L33/02 ,  H01L33/305 ,  H01S5/2209 ,  H01S5/221 ,  H01S5/2224 ,  H01S5/2226 ,  H01S5/2227 ,  H01S5/2272 ,  H01S5/3072

Abstract: A multi-layer dopant diffusion barrier is disclosed that effectively prevents dopant diffusion but does not contribute to parasitic pn junctions or parasitic capacitance. A multi-layer dopant diffusion barrier layer prevents dopant diffusion.

Abstract translation: 公开了一种多层掺杂剂扩散阻挡层，其有效地防止掺杂剂扩散，但不会对寄生pn结或寄生电容有贡献。 多层掺杂剂扩散阻挡层防止掺杂剂扩散。

公开(公告)号：US06664605B1

公开(公告)日：2003-12-16

申请号：US09539882

申请日：2000-03-31

Applicant: Yuliya A. Akulova ,  Sung-nee G. Chu ,  Michael Geva ,  Mark S. Hybertsen ,  Charles W. Lentz ,  Abdallah Ougazzaden

Inventor： Yuliya A. Akulova ,  Sung-nee G. Chu ,  Michael Geva ,  Mark S. Hybertsen ,  Charles W. Lentz ,  Abdallah Ougazzaden

IPC: H01L310232

CPC classification number: H01S5/227 ,  G02F1/025 ,  H01S5/221 ,  H01S5/2213 ,  H01S5/2226 ,  H01S5/3072 ,  H01S5/50

Abstract: A method for decreasing the diffusion of dopant atoms in the active region, as well as the interdiffuision of different types of dopant atoms among adjacent doped regions, of optoelectronic devices is disclosed. The method of the present invention employs a plurality of InAlAs and/or InGaAlAs layers to avoid the direct contact between the dopant atoms and the active region, and between the dopant atoms in adjacent blocking structures of optoelectronic devices. A semi-insulating buried ridge structure, as well as a ridge structure, in which the interdiffusion of different types of dopant atoms is suppressed are also disclosed.

Abstract translation: 公开了一种用于减少有源区中的掺杂剂原子的扩散以及相邻掺杂区中不同类型的掺杂剂原子在光电器件中的相互扩散的方法。 本发明的方法采用多个InAlAs和/或InGaAlAs层以避免掺杂剂原子与有源区之间以及光电子器件的相邻阻挡结构中的掺杂剂原子之间的直接接触。 还公开了抑制不同类型的掺杂剂原子的相互扩散的半绝缘掩埋隆起结构以及脊结构。

公开(公告)号：US06245144B1

公开(公告)日：2001-06-12

申请号：US09455136

申请日：1999-12-06

Applicant: Thomas C. Bitner ,  Chris W. Ebert ,  Michael Geva ,  Charles H. Joyner

Inventor： Thomas C. Bitner ,  Chris W. Ebert ,  Michael Geva ,  Charles H. Joyner

IPC: C30B2300

CPC classification number: C30B25/02 ,  C30B29/40

Abstract: A method of controlling the relative amounts of silicon dopant inside and outside of an enhanced growth region on an indium phosphide substrate using a metalorganic chemical vapor deposition (MOCVD) process. The method includes the steps of positioning the indium phosphide substrate in a reactor chamber, and defining an enhanced growth region on the substrate by depositing a dielectric mask on the substrate. The indium phosphide substrate is heated to a growth temperature of between about 600 and 630° C., and the pressure in the reactor chamber is adjusted to between about 40 and 80 Torr. A first gas contains a metalorganic compound comprising indium and a hydrogen carrier gas flow of between about 12 and 16 liters/minute, and a second gas containing a phosphide and a doping gas containing a silicon dopant at a flow rate of between are introduced into the reactor chamber. The first and second gases are mixed in the chamber and forced over the substrate in a laminar flow such that the mixed convection parameter is between about 0.31 and 0.33. An n-type indium phosphide epitaxial layer is thereby grown over the substrate by reacting the first with the second gas and thermally decomposing the carrier gas, whereby areas inside and outside of the growth enhanced region contain substantially the same amount of silicon dopant.

Abstract translation: 一种使用金属有机化学气相沉积（MOCVD）法在铟磷化物衬底上控制增强生长区内部和外部的硅掺杂剂的相对量的方法。 该方法包括以下步骤：将磷化铟基板定位在反应室中，并通过在基板上沉积介电掩模来限定衬底上增强的生长区域。 将磷化铟基底加热至约600至630℃的生长温度，并将反应器室中的压力调节至约40至80托。 第一气体含有包含铟的金属有机化合物和约12至16升/分钟的氢气载气流，并且将含有磷化物和含有硅掺杂剂的掺杂气体的第二气体以其流速引入到 反应室。 第一和第二气体在腔室中混合并以层流强迫在衬底上，使得混合对流参数在约0.31至0.33之间。 因此，通过使第一和第二气体反应而使衬底上的n型磷化铟外延层生长，并使载气热分解，由此生长增强区域内外的区域含有大致相同量的硅掺杂剂。

公开(公告)号：US6133125A

公开(公告)日：2000-10-17

申请号：US226399

申请日：1999-01-06

Applicant: Joseph Brian Seiler ,  Bryan Phillip Segner ,  Michael Geva ,  Cheng-Yu Tai ,  Erin Kathleen Byrne

Inventor： Joseph Brian Seiler ,  Bryan Phillip Segner ,  Michael Geva ,  Cheng-Yu Tai ,  Erin Kathleen Byrne

IPC: H01L21/223 ,  H01S5/30 ,  H01S5/32 ,  H01L21/22

CPC classification number: H01S5/305 ,  H01L21/2233 ,  H01S5/32

Abstract: A method for altering a dopant front profile of a dopant in a wafer is disclosed. An initial wafer is provided with an upper doped layer and a lower undoped layer. An oxide layer is grown over a portion of the wafer while a second portion of the wafer remains oxide-free. The wafer is then exposed to a substantially non-growth enhancement diffusion environment that contains the dopant at a given flow rate, but lacks additional materials which would cause growth on the exposed portions of wafer. After a predetermined amount of diffusion is allowed to occur, the wafer is removed from the diffusion environment and the oxide layer is removed.

Abstract translation: 公开了一种用于改变晶片中掺杂剂的掺杂剂前轮廓的方法。 初始晶片设置有上掺杂层和下未掺杂层。 在晶片的一部分上生长氧化物层，而晶片的第二部分保持无氧化。 然后将晶片暴露于以给定流速包含掺杂剂的基本上非增长的增强扩散环境，但是缺少会在晶片的暴露部分上生长的附加材料。 在允许发生预定量的扩散之后，从扩散环境去除晶片，并去除氧化物层。

公开(公告)号：US06542686B1

公开(公告)日：2003-04-01

申请号：US09648159

申请日：2000-08-25

Applicant: Michael Geva ,  Claude Lewis Reynolds, Jr. ,  Lawrence E. Smith

Inventor： Michael Geva ,  Claude Lewis Reynolds, Jr. ,  Lawrence E. Smith

IPC: G02B610

CPC classification number: G02B6/132 ,  G02B6/131

Abstract: The present invention provides an optoelectronic device and a method of manufacture therefor, that prevents dopant diffusion and controls the dopant concentration therein. The optoelectronic device includes an active region formed over a substrate, and an interface barrier layer and barrier layer located over the active region. The optoelectronic device further includes an upper cladding layer located over the interface barrier layer and the barrier layer. In an exemplary embodiment of the invention, the interface barrier layer is an indium phosphide interface barrier layer and the barrier layer is an indium gallium arsenide phosphide barrier layer.

Abstract translation: 本发明提供一种光电器件及其制造方法，其防止掺杂剂扩散并控制其中的掺杂剂浓度。 光电子器件包括在衬底上形成的有源区，以及位于有源区上方的界面阻挡层和阻挡层。 光电子器件还包括位于界面阻挡层和阻挡层之上的上覆层。 在本发明的示例性实施例中，界面阻挡层是磷化铟界面阻挡层，阻挡层是砷化镓磷化物阻挡层。