公开(公告)号：US20200264894A1

公开(公告)日：2020-08-20

申请号：US16869956

申请日：2020-05-08

Applicant: Silicon Motion, Inc.

Inventor： Chien-Chung CHUNG ,  Mei-Ting LIN ,  Chen-Ning YANG

IPC: G06F9/4401

Abstract: A data storage device waking up from a sleep mode rapidly is disclosed. The data storage device uses a controller to operate a non-volatile memory. The controller has a microprocessor and a volatile memory. The microprocessor loads boot code from the non-volatile memory to a not-always-on area of the volatile memory according to a script loaded on an always-on area of the volatile memory. The microprocessor executes the boot code loaded on the not-always-on area to load an in-system program from the non-volatile memory to the not-always-on area for execution of the in-system program. The script loaded on the always-on area is loaded from the non-volatile memory, and the non-volatile memory is searched to load the script to the always-on area in response to powering on a data storage device containing the non-volatile memory from a power-off state.

公开(公告)号：US20190114177A1

公开(公告)日：2019-04-18

申请号：US16016168

申请日：2018-06-22

Applicant: Silicon Motion, Inc.

Inventor： Chien-Chung CHUNG ,  Mei-Ting LIN ,  Chen-Ning YANG

IPC: G06F9/4401

CPC classification number: G06F9/4403 ,  G06F9/4418

Abstract: A data storage device waking up from a sleep mode rapidly is disclosed. The data storage device uses a controller to operate a non-volatile memory. The controller has a microprocessor and a volatile memory. The microprocessor loads boot code from the non-volatile memory to a not-always-on area of the volatile memory according to a script loaded on an always-on area of the volatile memory. The microprocessor executes the boot code loaded on the not-always-on area to load an in-system program from the non-volatile memory to the not-always-on area for execution of the in-system program.

公开(公告)号：US20190384872A1

公开(公告)日：2019-12-19

申请号：US16299216

申请日：2019-03-12

Applicant: Silicon Motion, Inc.

Inventor： Chien-Chung CHUNG

IPC: G06F17/50 ,  G06F12/0804

Abstract: A design technology for backup power of data storage device is disclosed. A development system for a data storage device includes a power supply fixture and a host. The host operates the power supply fixture and a data storage device. The data storage device has a non-volatile memory, a controller and a cache memory. The host operates the power supply fixture to power the data storage device, and operates the power supply fixture to trigger the controller to start a power-loss protection procedure at a first time point. According to the time taken by the power-loss procedure, the host optimizes the capacitance of a capacitor for implementation of a backup power supply to be equipped to the data storage device for production.

公开(公告)号：US20190087349A1

公开(公告)日：2019-03-21

申请号：US16028005

申请日：2018-07-05

Applicant: Silicon Motion, Inc.

Inventor： Chien-Chung CHUNG

IPC: G06F12/1009 ,  G06F12/02 ,  G06F3/06

Abstract: The data storage method includes selecting one of a plurality of blocks in a flash memory as an active block; dividing the active block into a plurality of virtual blocks; selecting and accessing one of the virtual blocks; and maintaining a mapping table corresponding to the selected virtual block. The mapping table records mapping information between a plurality of logical addresses and a plurality of physical addresses of the selected virtual block.

公开(公告)号：US20180373643A1

公开(公告)日：2018-12-27

申请号：US15869867

申请日：2018-01-12

Applicant: Silicon Motion, Inc.

Inventor： Chien-Chung CHUNG ,  Kuan-Hui LI ,  Yi-Chang HUANG

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/1041 ,  G06F2212/2022 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7206

Abstract: A data storage device includes a flash memory and a flash memory controller. The flash memory controller operates the flash memory to store data, and stores a mapping table to record the mapping information between a plurality of logical addresses and a plurality of physical addresses of the flash memory. The mapping table is divided into a plurality of groups. Some of the groups are categorized into a first type of trim group and some of the logical addresses of each of the groups of the first type of trim group are included in a trim command. The flash memory controller performs the trim on the groups of the first type of trim group.