公开(公告)号：US20220100373A1

公开(公告)日：2022-03-31

申请号：US17157368

申请日：2021-01-25

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F3/06 ,  G06F11/07

Abstract: The invention introduces a method, an apparatus and a non-transitory computer program product for storing data in flash memory. The method is performed by a processing unit when loading and executing program code of a flash translation layer to include: dividing storage space of a flash module into a first region and a second region; programming data belonging to a first partition type received from a host side into first physical blocks of the first region only; and programming data belonging to a second partition type received from the host side into the first physical blocks of the first region and the second physical blocks of the second region. With the region division and the policy for writing data into the regions in terms of data characteristics of different partition types, storage space of the flash module would be used more effective.

公开(公告)号：US20170109042A1

公开(公告)日：2017-04-20

申请号：US15286925

申请日：2016-10-06

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F3/06 ,  G06F12/0875 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0871 ,  G06F2206/1014 ,  G06F2212/1016 ,  G06F2212/466 ,  G06F2212/7201

Abstract: The present invention provides a data storage device including a flash memory and a random access memory. The flash memory has a data mapping table arranged to record a plurality of mapping relationships between the logical addresses and the physical addresses of a plurality of pages of the flash memory. The data mapping table is divided into a plurality of data mapping sets. The random access memory has a cache area, a sequential-order table, a reverse-order table and a cache-area mapping table. The cache area stores part of the data mapping sets. The cache-area mapping table records the set indexes of the data mapping sets of the cache area. The sequential-order table records the order that the data mapping sets are read from the cache area. The reverse-order table records the opposite order that the data mapping sets are read from the cache area.

公开(公告)号：US20160103622A1

公开(公告)日：2016-04-14

申请号：US14614442

申请日：2015-02-05

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F3/06 ,  G06F11/14

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0679 ,  G06F11/1415 ,  G06F2201/84 ,  G11C16/349

Abstract: In recovery operations performed after non-volatile memory devices (i.e., flash memories and so on) experience abnormal status, when unstable data pages are found, valid data pages are copied to another physical block from the original physical block directly and the original physical block is not utilized any more, in order to prevent from spreading error. Further, in order to accelerate the determination process, only partial data of a page is read and whether the page is a valid page is determined based on statistic, when finding out which page is a valid page.

Abstract translation: 在非易失性存储器件（即闪速存储器等）执行的恢复操作经历异常状态时，当发现不稳定的数据页时，有效数据页被直接从原始物理块复制到另一个物理块，并且原始物理块 不再被利用，以防止扩散错误。 此外，为了加速确定处理，只有当查找哪个页面是有效页面时，才基于统计量来仅读取页面的部分数据，并确定页面是否是有效页面。

公开(公告)号：US20200349065A1

公开(公告)日：2020-11-05

申请号：US16849235

申请日：2020-04-15

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16 ,  G06F11/30

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory controller is coupled to the memory device and is configured to access the memory device. In a garbage collection procedure, the memory controller is configured to select multiple spare memory blocks as destination memory blocks and move valid data stored in at least one source memory block into the destination memory blocks. In the garbage collection procedure, the memory controller is further configured to determine an attribute of each valid data and determine which destination memory block to move the valid data into according to the corresponding attribute. Valid data having the same attribute is moved to the same destination memory block.

公开(公告)号：US20170270047A1

公开(公告)日：2017-09-21

申请号：US15613342

申请日：2017-06-05

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F12/0875 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0871 ,  G06F12/0875 ,  G06F2206/1014 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/466 ,  G06F2212/7201

Abstract: The present invention provides a data storage device including a random access memory and a controller. The random access memory has a cache area. The controller loads a part of data mapping sets of the data mapping table on a plurality of sectors of the cache area, wherein any of the data mapping sets that has been read less than a predetermined number of times is defined as an infrequent data mapping set, and any of the data mapping sets that has been read more than the predetermined number of times is defined as a frequent data mapping set.

公开(公告)号：US20170139839A1

公开(公告)日：2017-05-18

申请号：US15331154

申请日：2016-10-21

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F12/1009 ,  G06F3/06

CPC classification number: G06F12/1009 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, wherein each of the blocks has a plurality of pages. The controller receives a plurality of write commands in a sequence, assigns a plurality of write sequence numbers to the write commands according to the sequence in which the write commands are received, and writes a plurality of data sectors and the write sequence numbers of the write commands into the pages of a first current block and a second current block of the blocks according to the write commands.

公开(公告)号：US20140250259A1

公开(公告)日：2014-09-04

申请号：US14100627

申请日：2013-12-09

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7208

Abstract: A data storage device and a FLASH memory control method with a cache space. The FLASH memory control method includes the following steps: using a plurality of channels to access a FLASH memory, wherein the FLASH memory has a plurality of blocks each with a plurality of pages, and the blocks are grouped to be accessed by the different channels; allocating a random access memory to provide a cache space, the cache space having a plurality of cache areas caching write data for the different channels, respectively; distributing the data issued from a host to correspond to the different channels; and reusing a latest-updated cache area of the cache space to cache write data when a logical address requested to be written with data is identical to a logical address that the latest-updated cache area corresponds to.

Abstract translation: 具有缓存空间的数据存储装置和FLASH存储器控制方法。 闪速存储器控制方法包括以下步骤：使用多个通道来访问闪速存储器，其中闪速存储器具有多个块，每个块具有多个页面，并且块被分组以被不同的通道访问; 分配随机存取存储器以提供高速缓存空间，所述高速缓存空间具有多个高速缓存区域，分别缓存用于不同信道的写入数据; 分配从主机发出的对应于不同频道的数据; 并且当请求写入数据的逻辑地址与最新更新的高速缓存区域对应的逻辑地址相同时，重新使用高速缓存空间的最新更新缓存区域来缓存写入数据。

公开(公告)号：US20210334209A1

公开(公告)日：2021-10-28

申请号：US17160850

申请日：2021-01-28

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F12/02 ,  G06F12/10

Abstract: The invention relates to a method, a non-transitory computer program product, and an apparatus for managing data storage. The method performed by a flash controller includes: obtaining information indicating a subregion to be activated, where the subregion is associated with a logical block address (LBA) range; triggering a garbage collection (GC) process being performed in background to migrate user data of all the or a portion of the LBA range associated with the subregion to continuous physical addresses in a flash device; and updating content of a plurality of entries associated with the subregion according to migration results, where each entry includes information indicating which physical address that user data of a corresponding logical address is physically stored in the flash device.

公开(公告)号：US20210318954A1

公开(公告)日：2021-10-14

申请号：US17026961

申请日：2020-09-21

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0891

Abstract: The invention relates to a non-transitory computer program product, a method and an apparatus for managing garbage collection process. The non-transitory computer program product includes program code to: determine source blocks to be processed, wherein each source block includes an invalid page; program user data of valid pages in the source blocks, whose quantity is less than a total number of pages in one first-type physical block, into empty pages in a second-type physical block, wherein the total number of pages in one first-type physical block is greater than a total number of pages in one second-type physical block; and fill remaining empty pages in the second-type physical block with dummy values.

公开(公告)号：US20200371952A1

公开(公告)日：2020-11-26

申请号：US16849214

申请日：2020-04-15

Applicant: Silicon Motion, Inc.

Inventor： Kuan-Yu KE

IPC: G06F12/1009

Abstract: A data storage device includes a memory device and a memory controller. The memory controller selects a predetermined memory block to receive data and records multiple logical addresses in a first mapping table. When the predetermined memory block is full, the memory controller edits a second mapping table based on the first mapping table. When editing the second mapping table, the memory controller determines whether M consecutive logical addresses have been recorded in the first mapping table. When the memory controller determines that M consecutive logical addresses have been recorded in the first mapping table, the memory controller edits the second mapping table according to a data compression rate (R), such that one or more fields, which correspond to one or more logical addresses recorded in the first mapping table, of the second mapping table are skipped and not edited. M and R are positive integers greater than 1.