公开(公告)号：US20240232067A1

公开(公告)日：2024-07-11

申请号：US18241996

申请日：2023-09-04

Applicant: Silicon Motion, Inc.

Inventor： Lu-Ting Wu ,  Shen-Ting Chiu ,  Te-Kai Wang ,  Po-Lin Wu

IPC: G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0238 ,  G06F12/1009

Abstract: A method for performing access management of a memory device in a predetermined communications architecture with aid of automatic parameter setting and associated apparatus are provided. The method may include: utilizing the memory controller to set at least one write booster static parameter of a write booster function of the memory device; utilizing the memory controller to perform device initialization corresponding to at least one initialization phase of the memory device; and after completing the device initialization corresponding to the at least one initialization phase, performing at least one flag-setting operation, for setting at least one write booster flag among a plurality of write booster flags of the write booster function, wherein the at least one write booster flag includes a first write booster flag acting as a write booster switch. The adaptive flag-setting operation includes setting the first write booster flag to enable the write booster function by default.

公开(公告)号：US20240143226A1

公开(公告)日：2024-05-02

申请号：US18220293

申请日：2023-07-11

Applicant: Silicon Motion, Inc.

Inventor： Po-Lin Wu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller performs a write operation in response to a write command, and during the write operation, the memory controller maintains a first quantity count value for counting a number of the predetermined memory block(s) that has/have been written with data, determine a number of the predetermined memory block(s) which is/are released in response to the write operation and maintains a second quantity count value based on this number. After the write operation, the memory controller performs a garbage collection and updates the first quantity count value based on the second quantity count value when determining that the host device has requested to perform a flush operation on the predetermined memory blocks.

公开(公告)号：US20240126473A1

公开(公告)日：2024-04-18

申请号：US18220288

申请日：2023-07-11

Applicant: Silicon Motion, Inc.

Inventor： Po-Lin Wu

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0614 ,  G06F3/064 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller performs a write operation in response to a write command issued by the host device, and during the write operation, the memory controller maintains a first quantity count value for counting a number of the predetermined memory block(s) that has/have been written with data, determines a number of the predetermined memory block(s) which is/are released in response to the write operation and maintains a second quantity count value based on this number. After the write operation, the memory controller updates the first quantity count value based on the second quantity count value when determining that the host device has requested to perform a flush operation on the predetermined memory blocks.

公开(公告)号：US20240143208A1

公开(公告)日：2024-05-02

申请号：US18219101

申请日：2023-07-07

Applicant: Silicon Motion, Inc.

Inventor： Po-Lin Wu

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0608 ,  G06F3/0656 ,  G06F3/0673

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks which include one or more spare memory blocks not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller obtains a total number of remaining erasable count of the memory blocks and determines a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks, a predetermined threshold and the total number of remaining erasable count of the memory blocks, and configures the number of the predetermined memory block(s) as the buffer according to the setting value.

公开(公告)号：US20240126463A1

公开(公告)日：2024-04-18

申请号：US18219705

申请日：2023-07-10

Applicant: Silicon Motion, Inc.

Inventor： Po-Lin Wu

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/0656 ,  G06F12/0253 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory blocks includes one or more spare memory blocks that are not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller is coupled to the memory device and configured to access the memory device. The memory controller is configured to determine a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks and a predetermined threshold, and configure the number of the predetermined memory block(s) as the buffer according to the setting value.