公开(公告)号：US20190103470A1

公开(公告)日：2019-04-04

申请号：US16137399

申请日：2018-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Chun-Ming Chen ,  Man-Tang Wu ,  Chen-Chih Fan ,  Nhan Do

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11546 ,  H01L29/08 ,  H01L29/66 ,  H01L27/11521

Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

公开(公告)号：US10608090B2

公开(公告)日：2020-03-31

申请号：US16137399

申请日：2018-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Chun-Ming Chen ,  Man-Tang Wu ,  Chen-Chih Fan ,  Nhan Do

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/265 ,  H01L27/11546 ,  H01L27/11521

Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.