公开(公告)号：US20220013531A1

公开(公告)日：2022-01-13

申请号：US17179057

申请日：2021-02-18

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei YANG ,  Man-Tang WU ,  Boolean FAN ,  Nhan DO

IPC: H01L27/11524 ,  G11C16/04 ,  H01L29/66

Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.

公开(公告)号：US20160218110A1

公开(公告)日：2016-07-28

申请号：US15003659

申请日：2016-01-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei YANG ,  Chun-Ming CHEN ,  Man-Tang WU ,  Feng ZHOU ,  Xian LIU ,  Chien-Sheng SU ,  Nhan DO

IPC: H01L27/115 ,  H01L21/306 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

Abstract translation: 一种通过形成间隔开的第一和第二区域形成存储器件的方法，其间具有通道区域，在沟道区域的第一部分上方形成浮栅，并与沟道区域的第一部分绝缘，形成控制栅极并与浮栅绝缘，形成 擦除栅极，并与第一区域绝缘，并且形成选通栅极，并与沟道区域的第二部分绝缘。 浮置栅极的形成包括在衬底上形成第一绝缘层，在第一绝缘层上形成第一导电层，并执行两个单独的蚀刻以形成通过第一导电层的第一和第二沟槽。 第一沟槽处的第一导电层的侧壁具有负斜率，第二沟槽处的第一导电层的侧壁是垂直的。