公开(公告)号：US20210005725A1

公开(公告)日：2021-01-07

申请号：US16868143

申请日：2020-05-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo XING ,  Chunming WANG ,  Guo Yong LIU ,  Melvin DIAO ,  Xian LIU ,  Nhan DO

IPC: H01L21/28 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/265

Abstract: A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.

公开(公告)号：US20160218110A1

公开(公告)日：2016-07-28

申请号：US15003659

申请日：2016-01-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei YANG ,  Chun-Ming CHEN ,  Man-Tang WU ,  Feng ZHOU ,  Xian LIU ,  Chien-Sheng SU ,  Nhan DO

IPC: H01L27/115 ,  H01L21/306 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

Abstract translation: 一种通过形成间隔开的第一和第二区域形成存储器件的方法，其间具有通道区域，在沟道区域的第一部分上方形成浮栅，并与沟道区域的第一部分绝缘，形成控制栅极并与浮栅绝缘，形成 擦除栅极，并与第一区域绝缘，并且形成选通栅极，并与沟道区域的第二部分绝缘。 浮置栅极的形成包括在衬底上形成第一绝缘层，在第一绝缘层上形成第一导电层，并执行两个单独的蚀刻以形成通过第一导电层的第一和第二沟槽。 第一沟槽处的第一导电层的侧壁具有负斜率，第二沟槽处的第一导电层的侧壁是垂直的。

公开(公告)号：US20210327512A1

公开(公告)日：2021-10-21

申请号：US17074103

申请日：2020-10-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo XING ,  Chunming WANG ,  Xian LIU ,  Nhan DO ,  Guangming LIN ,  Yaohua ZHU

IPC: G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.