公开(公告)号：US20090043993A1

公开(公告)日：2009-02-12

申请号：US12224671

申请日：2006-03-03

申请人： Simon Andrew Ford ,  Alastair Reid

发明人： Simon Andrew Ford ,  Alastair Reid

IPC分类号： G06F9/30

CPC分类号： G06F11/364 ,  G06F11/30

摘要： An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more signals occurring within the integrated circuit as a result of execution of the program. The monitoring logic stores configuration data, which can be software programmed in relation to the signals to be monitored. Further, the monitoring logic makes use of a Bloom filter which, for a value to be reviewed, performs a hash operation on that value in order to reference the configuration data to determine whether that value is either definitely not a value within the range or is potentially a value within the range of values. If the value is determined to be within the set of values, then a trigger signal is generated which can be used to trigger a further monitoring process.

摘要翻译： 提供一种集成电路以及检查在该集成电路内发生的一个或多个信号的值的方法。 集成电路包括用于执行程序的处理逻辑，以及作为执行程序的结果来检查在集成电路内发生的一个或多个信号的值的监视逻辑。 监视逻辑存储配置数据，其可以相对于待监视的信号进行软件编程。 此外，监视逻辑利用布隆过滤器，对于要被检查的值，对该值进行哈希运算以引用配置数据，以确定该值是否绝对不是该范围内的值，或者是 潜在的价值范围内的值。 如果该值被确定为在该值集合内，则产生可用于触发进一步监视过程的触发信号。

公开(公告)号：US08185724B2

公开(公告)日：2012-05-22

申请号：US12224671

申请日：2006-03-03

申请人： Simon Andrew Ford ,  Alastair Reid

发明人： Simon Andrew Ford ,  Alastair Reid

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F11/364 ,  G06F11/30

摘要： An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more signals occurring within the integrated circuit as a result of execution of the program. The monitoring logic stores configuration data, which can be software programmed in relation to the signals to be monitored. Further, the monitoring logic makes use of a Bloom filter which, for a value to be reviewed, performs a hash operation on that value in order to reference the configuration data to determine whether that value is either definitely not a value within the range or is potentially a value within the range of values. If the value is determined to be within the set of values, then a trigger signal is generated which can be used to trigger a further monitoring process.

摘要翻译： 提供一种集成电路以及检查在该集成电路内发生的一个或多个信号的值的方法。 集成电路包括用于执行程序的处理逻辑，以及作为执行程序的结果来检查在集成电路内发生的一个或多个信号的值的监视逻辑。 监视逻辑存储配置数据，其可以相对于待监视的信号进行软件编程。 此外，监视逻辑利用布隆过滤器，对于要检查的值，对该值执行散列操作，以引用配置数据，以确定该值是否绝对不是该范围内的值，或者是 潜在的价值范围内的值。 如果该值被确定为在该值集合内，则产生可用于触发进一步监视过程的触发信号。

公开(公告)号：US20100045682A1

公开(公告)日：2010-02-25

申请号：US12461418

申请日：2009-08-11

申请人： Simon Andrew Ford ,  Sean Tristram Ellis ,  Edward Charles Plowman

发明人： Simon Andrew Ford ,  Sean Tristram Ellis ,  Edward Charles Plowman

IPC分类号： G06F15/16 ,  G06F15/167

CPC分类号： G06F9/3877 ,  G06F9/30076 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3851 ,  G06T1/20

摘要： The present invention provides an improved technique for communicating between a central processing unit and a graphics processing unit of a data processing apparatus. Shared memory is provided which is accessible by the central processing unit and the graphics processing unit, and via which data structures are shareable between the central processing unit and the graphics processing unit. A bus is also provided via which the central processing unit, graphics processing unit and shared memory communicate. In accordance with a first mechanism of controlling the graphics processing unit, the central processing unit routes control signals via the bus. However, in addition, an interface is provided between the central processing unit and the graphics processing unit, and in accordance with an additional mechanism for controlling the graphics processing unit, the central processing unit provides control signals over the interface. This enables the GPU to continue to be used to handle large batches of graphics processing operations loosely coupled with the operations performed by the CPU, whilst through use of the additional mechanism it is also possible to employ the GPU to perform processing operations on behalf of the CPU in situations where those operations are tightly coupled with the operations performed by the CPU.

摘要翻译： 本发明提供了一种用于在数据处理装置的中央处理单元和图形处理单元之间进行通信的改进技术。 提供共享存储器，其可由中央处理单元和图形处理单元访问，并且经由该数据结构可在中央处理单元和图形处理单元之间共享。 还提供了一个中央处理单元，图形处理单元和共享存储器通信的总线。 根据控制图形处理单元的第一机构，中央处理单元经由总线传送控制信号。 然而，另外，在中央处理单元和图形处理单元之间提供接口，并且根据用于控制图形处理单元的附加机构，中央处理单元通过接口提供控制信号。 这使得GPU能够继续用于处理与CPU执行的操作松散耦合的大量图形处理操作，而通过使用附加机制，还可以使用GPU来代表CPU执行处理操作 在这些操作与CPU执行的操作紧密耦合的情况下，CPU。

公开(公告)号：US20080195856A1

公开(公告)日：2008-08-14

申请号：US11822149

申请日：2007-07-02

申请人： Simon Andrew Ford ,  Christopher James Styles

发明人： Simon Andrew Ford ,  Christopher James Styles

IPC分类号： G06F1/00

CPC分类号： G06F17/5054

摘要： A programmer 10 for a target device 16 is provided with a mass storage interface 12 for connecting to a host 2 so as to appear as a mass storage device to the host 2. A target programmer 18 is responsive to an image transferred from the host 2 to the programmer 10 to apply that image to the target device 16.

摘要翻译： 用于目标设备16的编程器10设置有大容量存储接口12，用于连接到主机2，以便作为海量存储设备呈现给主机2。 目标编程器18响应于从主机2传送到编程器10的图像，以将该图像应用于目标设备16。

公开(公告)号：US09557994B2

公开(公告)日：2017-01-31

申请号：US12588412

申请日：2009-10-14

申请人： Dominic Hugo Symes ,  Simon Andrew Ford

发明人： Dominic Hugo Symes ,  Simon Andrew Ford

IPC分类号： G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F7/48

CPC分类号： G06F9/30021 ,  G06F7/4812 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/345 ,  G06F9/382 ,  G06F9/3832 ,  G06F9/3873 ,  G06F9/3887 ,  G06F2207/3828

摘要： A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques.

摘要翻译： 提供了一种执行重排操作的数据处理装置和方法。 数据处理装置具有具有多个寄存器的寄存器数据存储器，每个寄存器存储多个数据元素。 处理电路响应于控制信号来对数据元素执行处理操作。 指令解码器响应于至少一个但不超过N个重排指令，其中N是奇数复数，以产生控制信号，以控制处理电路执行至少等同于：作为源数据元素的重新排列过程 存储在由所述至少一个重新布置指令识别的所述寄存器数据存储器的N个寄存器中的数据元素; 执行重排操作以在常规N路交错顺序和解交织顺序之间重新排列源数据元素，以便产生结果数据元素的序列; 并输出用于存储在寄存器数据存储器中的结果数据元素的序列。 这提供了一种特别有效的技术，用于执行N路交错和解交织操作，其中N是奇数，导致高性能，低能量消耗和降低的寄存器使用，与已知的现有技术相比。

公开(公告)号：US09405939B2

公开(公告)日：2016-08-02

申请号：US12285516

申请日：2008-10-07

申请人： Simon Andrew Ford ,  Christopher James Styles

发明人： Simon Andrew Ford ,  Christopher James Styles

IPC分类号： G06F15/16 ,  G06F21/80 ,  G06F21/56 ,  G06F21/78 ,  G06F21/71 ,  G06F21/12 ,  H04L29/06

CPC分类号： G06F17/302 ,  G06F17/30876 ,  G06F17/30896 ,  G06F21/123 ,  G06F21/56 ,  G06F21/71 ,  G06F21/78 ,  G06F21/80 ,  G06F2221/2129 ,  H04L63/061

摘要： A non-volatile mass storage device is provided comprising memory circuitry accessible to a host data processing device via a communication link. The non-volatile mass storage device comprises processing circuitry for locally accessing the memory circuitry of the file system and is capable of triggering generation of a file for storage on the memory circuitry by connection of the non-volatile mass storage device to the host data processing device. The generated file comprises information dependent upon a state of the non-volatile mass storage device. A corresponding method of operating a non-volatile mass storage device is provided and a computer program is provided for obtaining the information dependent upon the state of the non-volatile mass storage device, for locally accessing the memory circuitry and for generating the file for storage on the memory circuitry.

摘要翻译： 提供了一种非易失性大容量存储装置，其包括经由通信链路可由主机数据处理装置访问的存储器电路。 非挥发性大容量存储设备包括用于本地访问文件系统的存储器电路的处理电路，并且能够通过将非易失性大容量存储设备连接到主机数据处理来触发用于存储在存储器电路上的文件的生成 设备。 所生成的文件包括取决于非易失性大容量存储设备的状态的信息。 提供了操作非易失性大容量存储设备的相应方法，并且提供了一种计算机程序，用于根据非易失性大容量存储设备的状态获得信息，用于本地访问存储器电路并生成用于存储的文件 在存储器电路上。

公开(公告)号：US08484508B2

公开(公告)日：2013-07-09

申请号：US12656068

申请日：2010-01-14

申请人： Antony John Penton ,  Simon Andrew Ford ,  Andrew Christopher Rose

发明人： Antony John Penton ,  Simon Andrew Ford ,  Andrew Christopher Rose

IPC分类号： G06F11/00

CPC分类号： G06F11/1641

摘要： A data processing apparatus and method provide fault tolerance when executing a sequence of data processing operations. The data processing apparatus has processing circuitry for performing the sequence of data processing operations, and a redundant copy of that processing circuitry for operating in parallel with the processing circuitry, and for performing the same sequence of data processing operations. Error detection circuitry detects an error condition when output data generated by the processing circuitry differs from corresponding output data generated by the redundant copy. Shared prediction circuitry generates predicted data input to both the processing circuitry and the redundant copy, with the processing circuitry and redundant copy then performing speculative processing of one or more data processing operations in dependence on that predicted data. Each of the processing circuitry and the redundant copy include checking circuitry for determining whether the speculative processing was correct, and initiating corrective action if the speculative processing was not correct. By sharing the prediction circuitry rather than replicating it within both the processing circuitry and the redundant copy, significant area and power consumption benefits can be achieved without affecting the ability of the apparatus to detect faults.

摘要翻译： 数据处理装置和方法在执行数据处理操作的序列时提供容错。 数据处理装置具有用于执行数据处理操作序列的处理电路，以及用于与处理电路并联操作并用于执行相同数据处理操作序列的该处理电路的冗余副本。 当由处理电路产生的输出数据与由冗余副本产生的相应输出数据不同时，错误检测电路检测错误状况。 共享预测电路产生输入到处理电路和冗余副本的预测数据，处理电路和冗余副本然后根据该预测数据执行一个或多个数据处理操作的推测处理。 处理电路和冗余副本中的每一个包括用于确定推测性处理是否正确的检查电路，以及如果推测性处理不正确则启动校正动作。 通过共享预测电路而不是在处理电路和冗余副本中进行复制，可以在不影响设备检测故障的能力的情况下实现显着的面积和功耗优点。

公开(公告)号：US07647368B2

公开(公告)日：2010-01-12

申请号：US10930846

申请日：2004-09-01

申请人： Simon Andrew Ford ,  David James Seal ,  Wilco Dijkstra

发明人： Simon Andrew Ford ,  David James Seal ,  Wilco Dijkstra

IPC分类号： G06F7/38

CPC分类号： G06F9/30167 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3016 ,  G06F9/3017

摘要： Data processing apparatus and method perform data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to decode a data processing instruction in order to determine a corresponding data processing operation to be performed by the processing logic. The data processing instruction has an m-bit immediate value encoded therein. Further, constant generation logic is provided to perform a logical operation on the m-bit immediate value in order to generate an n-bit floating point constant for use as at least one input floating point data element for the processing logic when performing the corresponding data processing operation. The values “n” and “m” are integers, and n is greater than m. This approach provides a particularly efficient technique for generating floating point constants.

摘要翻译： 数据处理装置和方法对浮点数据元素执行数据处理操作。 数据处理装置具有用于对浮点数据元素执行数据处理操作的处理逻辑，以及可操作以对数据处理指令进行解码的解码逻辑，以便确定由处理逻辑执行的相应数据处理操作。 数据处理指令具有在其中编码的m位立即值。 此外，提供恒定生成逻辑以对m位立即值执行逻辑运算，以便在执行相应数据时产生用于处理逻辑的至少一个输入浮点数据元素的n位浮点常数 处理操作。 值“n”和“m”是整数，n大于m。 该方法提供了一种特别有效的生成浮点常数的技术。

公开(公告)号：US20080098208A1

公开(公告)日：2008-04-24

申请号：US11898360

申请日：2007-09-11

申请人： Alastair David Reid ,  Simon Andrew Ford ,  Yuan Lin

发明人： Alastair David Reid ,  Simon Andrew Ford ,  Yuan Lin

IPC分类号： G06F9/38

CPC分类号： G06F11/362 ,  G06F11/3636

摘要： A method is disclosed for transforming a portion of a computer program comprising a list of sequential instructions comprising control code and data processing code and a program separation indicator indicating a point where said sequential instructions may be divided to form separate sections that are capable of being separately executed and that each comprise different data processing code. The m method comprises the steps of: (i) analysing said portion of said program to determine if said sequential instructions can be divided at said point indicated by said program separation indicator and in response to determining that it can: (iia) providing data communication between said separate sections indicated by said program separation indicator, such that said separate sections can be decoupled from each other, such that at least one of said sections is capable of being separately executed by an execution mechanism that is separate from an execution mechanism executing another of said separate sections, said at least one of said sections being capable of generating data and communicating said data to at least one other of said separate sections; and in response to determining it can not: (iib) not performing step (iia). If step (iia) is not performed then a warning may be output, or the program may be amended so it can be separated at that point, or the program separation indicator may be removed and the sections that were to be separated merged.

摘要翻译： 公开了一种用于变换计算机程序的一部分的方法，该方法包括包括控制代码和数据处理代码的顺序指令的列表，以及指示所述顺序指令可被划分的点的程序分离指示器，以形成能够分开的分开的部分 并且每个都包括不同的数据处理代码。 m方法包括以下步骤：（i）分析所述程序的所述部分，以确定所述顺序指令是否可以由所述程序分离指示符指示的所述点被分割，并且响应于确定它可以：（i）提供数据通信 在由所述程序分离指示符指示的所述单独部分之间，使得所述单独部分可以彼此解耦，使得所述部分中的至少一个能够由执行机构分离执行，所述执行机制与执行另一部分的执行机制分离 所述分段中的至少一个能够生成数据并将所述数据传送到所述分离部分中的至少另一个部分; 并且响应于确定它不能：（iib）不执行步骤（iia）。 如果没有执行步骤（iia），则可以输出警告，或者可以修改程序，以便可以在该点分离，或者可以移除程序分离指示符，并且要分离的部分合并。

公开(公告)号：US08621336B2

公开(公告)日：2013-12-31

申请号：US12222085

申请日：2008-08-01

申请人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

发明人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

IPC分类号： G06F11/00

CPC分类号： G06F11/1064

摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.