公开(公告)号：US08621336B2

公开(公告)日：2013-12-31

申请号：US12222085

申请日：2008-08-01

申请人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

发明人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

IPC分类号： G06F11/00

CPC分类号： G06F11/1064

摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.

公开(公告)号：US08335908B2

公开(公告)日：2012-12-18

申请号：US12801926

申请日：2010-07-01

申请人： Alex James Waugh

发明人： Alex James Waugh

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/681 ,  Y02D10/13

摘要： Memory address translation buffering circuitry is provided comprising a primary storage bank and a secondary storage bank. Storage bank accessing circuitry is provided to perform a parallel lookup of the primary storage bank and the secondary storage bank for virtual to physical address translation entries. Buffering management circuitry is configured to transfer an address translation entry between the primary storage bank and the secondary storage bank dependent upon an occupancy level of at least one of the primary storage bank and secondary storage bank.

摘要翻译： 提供了存储器地址转换缓冲电路，其包括主存储体和辅助存储体。 提供存储库访问电路以执行用于虚拟到物理地址转换条目的主存储库和辅助存储库的并行查找。 缓冲管理电路被配置为根据主存储库和辅助存储库中的至少一个的占用水平在主存储库和次存储组之间传送地址转换条目。

公开(公告)号：US20100250802A1

公开(公告)日：2010-09-30

申请号：US12382939

申请日：2009-03-26

申请人： Alex James Waugh ,  Andrew Christopher Rose

发明人： Alex James Waugh ,  Andrew Christopher Rose

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F13/4022

摘要： A data processing apparatus and method are provided for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices. The series of access requests include one or more write access requests, each write access request specifying a write operation to be performed by an addressed slave device, and each issued write access request being a pending write access request until the write operation has been completed by the addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry is responsive to receipt of a write access request to be issued by the processing circuitry, to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value in one of the counters. On completion of each write access request by the addressed slave device, the update circuitry performs a further update process to remove the record of that completed write access request from the pending write access history storage. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference the pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry uses a combination of buffers and counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.

摘要翻译： 提供了一种数据处理装置和方法，用于对由一个或多个从设备处理的处理电路发出的一系列访问请求进行危险检测。 一系列访问请求包括一个或多个写访问请求，每个写访问请求指定要由寻址的从设备执行的写操作，并且每个发出的写访问请求是待处理写访问请求，直到写操作已经被 寻址的从设备。 危险检测电路包括具有至少一个缓冲器和至少一个用于保持每个未决写入访问请求的记录的计数器的待决写入访问历史存储器。 更新电路响应于由处理电路发出的写入访问请求的接收，以执行更新处理以将该写入访问请求识别为缓冲器之一中的待决写入访问请求，并且如果另一待处理写入的标识 访问请求被该更新过程覆盖，以增加其中一个计数器中的计数值。 在由所寻址的从设备完成每次写入访问请求后，更新电路执行进一步的更新处理，以从挂起的写入访问历史存储中移除该完成的写访问请求的记录。 危害检查电路然后对由处理电路发出的访问请求的至少一个子集作出响应，以引用待处理写入访问历史存储，以便确定是否发生危险状况。 更新电路使用缓冲器和计数器的组合来保持每个待处理写入访问请求的记录的方式提供了关于已知的现有技术的改进的性能，而没有与增加缓冲器数量相关联的硬件成本。

公开(公告)号：US20090164727A1

公开(公告)日：2009-06-25

申请号：US12004476

申请日：2007-12-21

申请人： Antony John Penton ,  Alex James Waugh ,  Andrew Christopher Rose ,  Paul Stanley Hughes

发明人： Antony John Penton ,  Alex James Waugh ,  Andrew Christopher Rose ,  Paul Stanley Hughes

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F11/1064 ,  G11C15/00 ,  G11C29/42 ,  G11C29/76 ,  G11C2029/0409 ,  G11C2029/0411

摘要： A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. The cache storage comprising data storage having a plurality of cache lines for storing data values, and address storage having a plurality of entries, with each entry identifying for an associated cache line an address indication value, and each entry having associated error data. In response to an access request, a lookup procedure is performed to determine with reference to the address indication value held in at least one entry of the address storage whether a hit condition exists in one of the cache lines. Further, error detection circuitry determines with reference to the error data associated with the at least one entry of the address storage whether an error condition exists for that entry. Additionally, cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of the error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. Further, the error detection circuitry causes a clean and invalidate operation to be performed in respect of the specific cache line, and the access request is then re-performed. The cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from the lookup procedure. This mechanism provides a very simple and effective mechanism for handling hard errors that manifest themselves within a cache during use, so as to ensure correct operation of the cache in the presence of such hard errors. Further, the technique can be employed not only in association with write through caches but also write back caches, thus providing a very flexible solution.

公开(公告)号：US09003123B2

公开(公告)日：2015-04-07

申请号：US13532904

申请日：2012-06-26

申请人： Alex James Waugh ,  Matthew Lee Winrow

发明人： Alex James Waugh ,  Matthew Lee Winrow

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F9/45

CPC分类号： G06F12/0862 ,  G06F8/4442

摘要： An instruction cache stores cacheable instructions for access by a processing circuitry, the instruction cache having a data storage comprising a plurality of cache lines and a tag storage comprising a plurality of tag entries, each cache line for storing instruction data specifying a plurality of cacheable instructions, and each tag entry for storing an address identifier for the instruction data stored in an associated cache line. The instruction cache including valid flag storage for identifying whether each cache line is valid. Instruction cache control circuitry is arranged to store within a selected cache line of the data storage the instruction data for a plurality of cacheable instructions as retrieved from memory, to store within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and to identify that selected cache line as valid within the valid flag storage.

摘要翻译： 指令高速缓存存储用于由处理电路进行访问的高速缓存指令，指令高速缓存具有包括多个高速缓存线的数据存储器和包括多个标签条目的标签存储器，每条高速缓存行用于存储指定多个可缓存指令的指令数据 以及每个标签条目，用于存储存储在相关联的高速缓存行中的指令数据的地址标识符。 指令高速缓存包括用于识别每个高速缓存行是否有效的有效标志存储。 指令高速缓存控制电路被设置为在数据存储器的所选高速缓存行内存储用于从存储器检索的多个可高速缓存指令的指令数据，以存储与所选择的高速缓存行相关联的标签条目中存储的指令的地址标识符 数据，并将所选择的高速缓存行标识为在有效标志存储中有效。

公开(公告)号：US20120005454A1

公开(公告)日：2012-01-05

申请号：US12801926

申请日：2010-07-01

申请人： Alex James Waugh

发明人： Alex James Waugh

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/681 ,  Y02D10/13

摘要： Memory address translation buffering circuitry is provided comprising a primary storage bank and a secondary storage bank. Storage bank accessing circuitry is provided to perform a parallel lookup of the primary storage bank and the secondary storage bank for virtual to physical address translation entries. Buffering management circuitry is configured to transfer an address translation entry between the primary storage bank and the secondary storage bank dependent upon an occupancy level of at least one of the primary storage bank and secondary storage bank.

公开(公告)号：US08977820B2

公开(公告)日：2015-03-10

申请号：US12004476

申请日：2007-12-21

申请人： Antony John Penton ,  Alex James Waugh ,  Andrew Christopher Rose ,  Paul Stanley Hughes

发明人： Antony John Penton ,  Alex James Waugh ,  Andrew Christopher Rose ,  Paul Stanley Hughes

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F11/10 ,  G11C29/42 ,  G11C29/00 ,  G11C15/00 ,  G11C29/04

CPC分类号： G06F12/0864 ,  G06F11/1064 ,  G11C15/00 ,  G11C29/42 ,  G11C29/76 ,  G11C2029/0409 ,  G11C2029/0411

摘要： A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. Cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of an error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. A clean and invalidate operation is performed in respect of the specific cache line, and the access request is then re-performed. Cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from a lookup procedure.

摘要翻译： 提供了一种用于处理在数据处理装置的高速缓存中出现的硬错误的数据处理装置和方法。 提供具有至少一个记录的缓存位置避免存储，其中每个记录用于存储标识特定高速缓存行的高速缓存行标识符。 在检测到错误状况时，分配缓存位置避免存储中的记录之一以存储与检测到错误条件的条目相关联的特定高速缓存行的高速缓存行标识符。 针对特定高速缓存线执行干净且无效的操作，然后重新执行访问请求。 缓存访问电路被布置为排除在高速缓存位置中识别的任何特定高速缓存行，避免存储从查找过程。

公开(公告)号：US20130346698A1

公开(公告)日：2013-12-26

申请号：US13532904

申请日：2012-06-26

申请人： Alex James Waugh ,  Matthew Lee Winrow

发明人： Alex James Waugh ,  Matthew Lee Winrow

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F8/4442

摘要： A data processing apparatus and method, the apparatus including processing circuitry for executing a sequence of instructions, each instruction having an associated memory address and the sequence of instructions including cacheable instructions whose associated memory addresses are within a cacheable memory region. Instruction cache control circuitry is arranged to store within a selected cache line of a data storage the instruction data for a plurality of cacheable instructions as retrieved from memory, to store within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and to identify that selected cache line as valid within the valid flag storage. Control state circuitry maintains a record of the chosen cache line in which said data of a predetermined data type has been written, so that upon receipt of a request for that data it can then be provided from the instruction cache.

摘要翻译： 一种数据处理装置和方法，该装置包括用于执行指令序列的处理电路，每个指令具有相关联的存储器地址和指令序列，包括其相关联的存储器地址在可高速缓存存储器区域内的可缓存指令。 指令高速缓存控制电路被布置为在数据存储器的所选高速缓存行内存储用于从存储器检索的多个可高速缓存指令的指令数据，以存储与所选择的高速缓存行相关联的标签条目中存储的指令的地址标识符 数据，并将所选择的高速缓存行标识为在有效标志存储中有效。 控制状态电路保持所选择的高速缓存行的记录，其中已经写入了预定数据类型的所述数据，使得在接收到对该数据的请求后，可以从指令高速缓存提供该记录。

公开(公告)号：US20090044086A1

公开(公告)日：2009-02-12

申请号：US12222085

申请日：2008-08-01

申请人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

发明人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

IPC分类号： G06F11/30

CPC分类号： G06F11/1064

摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.

摘要翻译： 提供了一种数据处理装置，包括用于执行数据处理操作的处理电路，用于在执行数据处理操作时存储由处理电路进行访问的数据值的组合关联存储装置，用于对存储装置的每次访问执行的错误检测电路， 对所访问的数据值的错误检测操作，以及与存储设备相关联的用于执行一个或多个维护操作的维护电路。 处理电路被布置为向维护电路发出指示存储设备内的至少一个特定物理位置的错误检测维护请求，并且维护电路响应于错误检测维护请求，以对至少一个虚拟访问 在所述存储设备内的至少一个特定的物理位置，并且为所述处理电路提供由所述错误检测电路针对所述至少一个虚拟访问执行的错误检测操作导出的错误状态信息。

公开(公告)号：US07941584B2

公开(公告)日：2011-05-10

申请号：US12382939

申请日：2009-03-26

申请人： Alex James Waugh ,  Andrew Christopher Rose

发明人： Alex James Waugh ,  Andrew Christopher Rose

IPC分类号： G06F13/00

CPC分类号： G06F13/4022

摘要： A data processing apparatus and method are provided for performing hazard detection in a series of access requests issued by processing circuitry for handling by one or more slaves. The requests include one or more write access requests to be performec by an addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry responds receipt of a write access request to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value a counter. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry jses a combination of buffers aid counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.

摘要翻译： 提供了一种数据处理装置和方法，用于在由一个或多个从属装置处理的处理电路发出的一系列访问请求中执行危险检测。 请求包括由寻址的从设备执行的一个或多个写访问请求。 危险检测电路包括具有至少一个缓冲器和至少一个用于保持每个未决写入访问请求的记录的计数器的待决写入访问历史存储器。 更新电路响应接收写入访问请求以执行更新处理，以将该写入访问请求识别为缓冲器之一中的待决写入访问请求，并且如果该更新过程覆盖另一待决写入访问请求的标识，则 增加计数值计数器。 危害检查电路然后响应于要由处理电路发出的访问请求的至少一个子集，以参考未决的写入访问历史存储，以便确定是否发生危险状况。 更新电路以缓冲器组合的方式辅助计数器以保持每个未决写入访问请求的记录提供了相对于已知的现有技术的改进的性能，而没有与增加缓冲器数量相关联的硬件成本。