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1.发明授权Systems and methods for executing across at least one memory barrier employing speculative fills 有权通过使用投机填充的至少一个记忆障碍执行的系统和方法公开(公告)号：US07360069B2
公开(公告)日：2008-04-15
申请号：US10756639
申请日：2004-01-13
IPC分类号： G06F9/00
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3863 , G06F12/0815 , G06F12/0859
摘要： Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.
摘要翻译： 提供多处理器系统和方法。 一个实施例涉及一种多处理器系统，其可以包括具有处理器流水线的处理器，处理器流水线通过至少一个存储器障碍执行程序指令，其中数据来自响应于源请求而提供的推测数据填充，以及保留执行负载的日志 与执行的程序指令相关联的指令条目。 如果在与执行的执行加载指令的历元不同的时期中，与推测数据填充的数据相关联的高速缓存行没有被无效，那么执行的加载指令条目可能会被停止。
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公开(公告)号：US07856534B2
公开(公告)日：2010-12-21
申请号：US10758352
申请日：2004-01-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F12/0831
摘要： One disclosed embodiment may comprise a system that includes a home node that provides a transaction reference to a requester in response to a request from the requester. The requester provides an acknowledgement message to the home node in response to the transaction reference, the transaction reference enabling the requester to determine an order of requests at the home node relative to the request from the requester.
摘要翻译： 一个公开的实施例可以包括系统，其包括家庭节点，其响应于来自请求者的请求向请求者提供事务参考。 请求者响应于事务参考向家庭节点提供确认消息，事务参考使得请求者能够相对于来自请求者的请求确定家庭节点处的请求的顺序。
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公开(公告)号：US07340565B2
公开(公告)日：2008-03-04
申请号：US10755919
申请日：2004-01-13
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0828 , G06F12/084 , G06F2212/507
摘要： Multiprocessor systems and methods are disclosed. One embodiment may comprise a plurality of processor cores. A given processor core may be operative to generate a request for desired data in response to a cache miss at a local cache. A shared cache structure may provide at least one speculative data fill and a coherent data fill of the desired data to at least one of the plurality of processor cores in response to a request from the at least one processor core. A processor scoreboard arbitrates the requests for the desired data. A speculative data fill of the desired data is provided to the at least one processor core. The coherent data fill of the desired data may be provided to the at least one processor core in a determined order.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括多个处理器核。 给定的处理器核心可以用于响应于本地高速缓存处的高速缓存未命中而产生对期望数据的请求。 响应于来自至少一个处理器核心的请求，共享高速缓存结构可以向所述多个处理器核心中的至少一个提供期望数据的至少一个推测数据填充和相干数据填充。 处理器记分板对所需数据的请求进行仲裁。 将所需数据的推测数据填充提供给至少一个处理器核。 期望数据的相干数据填充可以以确定的顺序提供给至少一个处理器核心。
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4.发明授权System and method for read migratory optimization in a cache coherency protocol 失效缓存一致性协议中读取迁移优化的系统和方法公开(公告)号：US07143245B2
公开(公告)日：2006-11-28
申请号：US10761044
申请日：2004-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0828 , G06F2212/2542
摘要： A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to the source broadcast to provide the data to the second node and transition the state associated with the data at the first node from the D-state to an O-state without concurrently updating memory. An S-state is associated with the data at the second node.
摘要翻译： 系统包括包括具有相关D状态的数据的第一节点和用于提供请求数据的源广播的第二节点。 第一节点响应于源广播而操作以向第二节点提供数据，并将与第一节点处的数据相关联的状态从D状态转换到O状态，而不同时更新存储器。 S状态与第二节点处的数据相关联。
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5.发明授权Consistency evaluation of program execution across at least one memory barrier 有权至少一个记忆障碍的程序执行的一致性评估公开(公告)号：US08301844B2
公开(公告)日：2012-10-30
申请号：US10756534
申请日：2004-01-13
IPC分类号： G06F13/38
CPC分类号： G06F12/0808
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system including a processor that executes program instructions across at least one memory barrier. A request engine may provide an updated data fill corresponding to an invalid cache line. The invalid cache line may be associated with at least one executed load instruction. A load compare component may compare the invalid cache line to the updated data fill to evaluate the consistency of the at least one executed load instruction.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括多处理器系统，其包括跨越至少一个存储器屏障执行程序指令的处理器。 请求引擎可以提供对应于无效高速缓存行的更新的数据填充。 无效高速缓存行可以与至少一个执行的加载指令相关联。 负载比较组件可以将无效高速缓存行与更新的数据填充进行比较，以评估至少一个执行的加载指令的一致性。
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6.发明授权System and method for resolving transactions in a cache coherency protocol 有权用于解决高速缓存一致性协议中的事务的系统和方法公开(公告)号：US08176259B2
公开(公告)日：2012-05-08
申请号：US10760813
申请日：2004-01-20
IPC分类号： G06F13/38
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0828
摘要： A system comprises a first node that employs a source broadcast protocol to initiate a transaction. The first node employs a forward progress protocol to resolve the transaction if the source broadcast protocol cannot provide a deterministic resolution of the transaction.
摘要翻译： 系统包括采用源广播协议来发起事务的第一节点。 如果源广播协议不能提供事务的确定性分辨率，则第一节点采用前进进程协议来解决事务。
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7.发明授权Multi-processor systems and methods for backup for non-coherent speculative fills 失效用于非相干投机填充的多处理器系统和备份方法公开(公告)号：US07406565B2
公开(公告)日：2008-07-29
申请号：US10756637
申请日：2004-01-13
CPC分类号： G06F9/383 , G06F9/384 , G06F9/3842 , G06F9/3863 , G06F12/0815
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the speculative fill. The backup system may initiate a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline may continue execution of program instructions if the speculative fill is determined to be coherent.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括多处理器系统，其包括具有处理器流水线的处理器，处理器流水线通过响应于源请求而提供的来自推测填充的数据执行程序指令，以及备份系统，其保留与先前处理器执行状态相关联的信息 对应于与投机填充相关联的指令。 如果确定推测填充是非相干的，则备用系统可以启动处理器管线的备份到先前的处理器执行状态，并且如果确定推测填充是相干的，则处理器流水线可以继续执行程序指令。
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8.发明授权System and method for conflict responses in a cache coherency protocol with ordering point migration 有权具有排序点迁移的缓存一致性协议中的冲突响应的系统和方法公开(公告)号：US07395374B2
公开(公告)日：2008-07-01
申请号：US10760651
申请日：2004-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.
摘要翻译： 公开了用于不同高速缓存一致性协议之间的交互的系统和方法。 一个系统可以包括家庭节点，其在第一高速缓存一致性协议中从第一节点接收对数据的请求。 第二节点向来自家节点的数据的请求提供冲突响应。 冲突响应指示数据的排序点根据与第一高速缓存一致性协议不同的第二高速缓存一致性协议进行迁移。
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公开(公告)号：US07376794B2
公开(公告)日：2008-05-20
申请号：US10756636
申请日：2004-01-13
CPC分类号： G06F12/0822
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source request by the source processor, and a coherent signal generated by the multi-processor system that provides an indication of which data fill of the at least one data fill is a coherent data fill.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括多处理器系统，其包括响应于源处理器的源请求而提供给源处理器的至少一个数据填充，以及由多处理器系统生成的相干信号，其提供哪个数据填充的指示 所述至少一个数据填充是相干数据填充。
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10.发明授权System and method for responses between different cache coherency protocols 有权用于不同缓存一致性协议之间的响应的系统和方法公开(公告)号：US07177987B2
公开(公告)日：2007-02-13
申请号：US10760436
申请日：2004-01-20
CPC分类号： G06F12/0831 , G06F12/0828 , G06F2212/2542
摘要： Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests provided according to a second cache coherency protocol, the second cache coherency protocol being different from the first cache coherency protocol. The first node provides a response to a given one of the requests to the first node that varies based on the condition detected by the detector.
摘要翻译： 公开了用于为不同的高速缓存一致性协议提供响应的系统和方法。 一个实施例可以包括包括采用第一高速缓存一致性协议的第一节点的系统。 与第一节点相关联的检测器基于由第一节点向根据第二高速缓存一致性协议提供的请求提供的响应来检测条件，第二高速缓存一致性协议不同于第一高速缓存一致性协议。 第一节点提供对根据检测器检测到的条件而变化的对第一节点的给定一个请求的响应。
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