公开(公告)号：US11776501B2

公开(公告)日：2023-10-03

申请号：US17991508

申请日：2022-11-21

Applicant: Snap Inc.

Inventor： Stewart S. Taylor

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G2310/0291 ,  G09G2310/08

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

公开(公告)号：US20240379074A1

公开(公告)日：2024-11-14

申请号：US18784312

申请日：2024-07-25

Applicant: Snap Inc.

Inventor： Stewart S. Taylor

IPC: G09G3/36

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

公开(公告)号：US12087248B2

公开(公告)日：2024-09-10

申请号：US18450811

申请日：2023-08-16

Applicant: Snap Inc.

Inventor： Stewart S. Taylor

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G2310/0291 ,  G09G2310/08

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

公开(公告)号：US20230395037A1

公开(公告)日：2023-12-07

申请号：US18450811

申请日：2023-08-16

Applicant: Snap Inc.

Inventor： Stewart S. Taylor

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G2310/08 ,  G09G2310/0291

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LcoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

公开(公告)号：US11580927B2

公开(公告)日：2023-02-14

申请号：US17413621

申请日：2020-07-01

Applicant: Snap Inc.

Inventor： Stewart S. Taylor

IPC: G09G3/36

Abstract: A system, circuit, and method for implementing a low power common electrode voltage for a display (e.g., LCoS display) having transistors with low to moderate breakdown voltages may include a first and a second low voltage amplifier, wherein the first amplifier generates a pixel voltage and the second amplifier generates a predetermined voltage. The circuit may include a common electrode circuit coupled to the first and second amplifier to generate a common electrode voltage. Particularly, the circuit may include a control circuit coupled to the common electrode circuit, wherein, during a first phase, the control circuit selectively controls the common electrode circuit to generate a low common electrode voltage based upon a negative value of the predetermined voltage. Further, during a second phase, the control circuit selectively controls the common electrode circuit to generate a high common electrode voltage based upon the sum of the predetermined voltage and the pixel voltage.

公开(公告)号：US20240291453A1

公开(公告)日：2024-08-29

申请号：US18427535

申请日：2024-01-30

Applicant: Snap Inc.

Inventor： Stewart S. Taylor

IPC: H03F3/45 ,  H03G1/00

CPC classification number: H03F3/45748 ,  H03F3/45219 ,  H03F3/45273 ,  H03G1/0023 ,  H03G1/0029 ,  H03F2200/375 ,  H03F2203/45028

Abstract: An amplifier circuit including a first folded double cascode stage configured to receive a differential input signal at a first pair of input transistors and generate a first drive signal, a second folded double cascode stage configured to receive the differential input signal at a second pair of input transistors and generate a second drive signal, and an output stage. The output stage includes a PMOS common-source output transistor configured to receive the first drive signal at its gate, and an NMOS common-source output transistor configured to receive the first drive signal at its gate, the PMOS common-source output transistor and NMOS common-source output transistor being jointly configured to generate an output signal based on the first drive signal and the second drive signal.

公开(公告)号：US20230377532A1

公开(公告)日：2023-11-23

申请号：US18252462

申请日：2020-12-10

Applicant: Snap Inc.

Inventor： James L. Sanford ,  Howard V. Goetz ,  Stewart S. Taylor

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G2300/0838 ,  G09G2300/0857 ,  G09G2300/0828

Abstract: Systems and methods for a digital pixel circuit for liquid crystal displays are provided. The design includes a dual-voltage pixel design, a two-transistor level-shift circuit design, self-adjusting transistor bias circuitry; and an optional on-chip test-array to determine die-specific design-center values for critical transistor leakage and threshold parameters. Level shift design simplicity, small pixel pitch, and applicability for small display applications such as microdisplays, are among the various benefits and advantages obtained.

公开(公告)号：US12249294B2

公开(公告)日：2025-03-11

申请号：US18252462

申请日：2020-12-10

Applicant: Snap Inc.

Inventor： James L. Sanford ,  Howard V. Goetz ,  Stewart S. Taylor

IPC: G09G3/36

Abstract: Systems and methods for a digital pixel circuit for liquid crystal displays are provided. The design includes a dual-voltage pixel design, a two-transistor level-shift circuit design, self-adjusting transistor bias circuitry; and an optional on-chip test-array to determine die-specific design-center values for critical transistor leakage and threshold parameters. Level shift design simplicity, small pixel pitch, and applicability for small display applications such as microdisplays, are among the various benefits and advantages obtained.