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公开(公告)号：US20190140651A1
公开(公告)日：2019-05-09
申请号：US16238092
申请日：2019-01-02
Applicant: SOCIONEXT INC.
Inventor： Hajime SATO , Kenta ARUGA
CPC classification number: H03L7/095 , H03L7/087 , H03L7/099 , H03L7/0995 , H03L7/0997 , H03L7/101 , H03L7/18 , H03L2207/06
Abstract: A PFD outputs a detection signal based on a phase difference or a frequency difference between a reference signal and a feedback signal, a charge pump circuit outputs a pulse signal based on the detection signal, and a loop filter outputs a control voltage based on the pulse signal. A VCO includes a ring oscillator where a plurality of delay element units, which include a plurality of delay elements (for example, inverter circuits) connected in parallel, are connected in series in a ring, controls the frequency of the output signal of the ring oscillator based on the control voltage, and controls the phase of the output signal of the ring oscillator by controlling the active number of delay elements, out of the plurality of delay elements, based on the detection signal. A frequency divider circuit generates and outputs a feedback signal by dividing the frequency of the output signal.
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2.发明公开公开(公告)号：US20230261664A1
公开(公告)日：2023-08-17
申请号：US18301708
申请日：2023-04-17
Applicant: Socionext Inc.
Inventor： Kenta ARUGA , Takeshi TAKAYAMA , Shota HINO
CPC classification number: H03M1/1245 , H03M1/462
Abstract: A sampling circuit includes: a first capacitor including a first terminal and a second terminal; a second capacitor including a third terminal and a fourth terminal; a first input node configured to receive a first input voltage that is one of a differential input voltage; a second input node configured to receive a second input voltage that is the other of the differential input voltage; a first switch circuit configured to be provided between the first input node and the first terminal; a second switch circuit configured to be provided between the second input node and the third terminal; a third switch circuit configured to be provided between the first terminal and the third terminal; and a fourth switch circuit configured to be provided between the second terminal and the fourth terminal.
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公开(公告)号：US20230163797A1
公开(公告)日：2023-05-25
申请号：US18057054
申请日：2022-11-18
Applicant: Socionext Inc.
Inventor： Kenta ARUGA , Takashi MIYAZAKI , Daisuke KIMURA , Yasuhiro MAJIMA , Shunichiro MASAKI , Shunsuke HIRANO
CPC classification number: H04B1/10 , H04L27/0008
Abstract: A processing circuit includes: a clock generating circuit configured to generate, based on a reference clock signal and a frequency division ratio, a first clock signal; a frequency dividing and delay circuit configured to generate a second clock signal to have a first phase difference with the reference clock signal by dividing the frequency of the first clock signal and delaying the first clock signal based on a phase shift set signal and the frequency division ratio; an analog-to-digital converter circuit configured to convert an analog signal into a digital signal based on the first clock signal and a conversion trigger signal indicating a sampling period and a conversion period; and a control circuit configured to generate the conversion trigger signal to have the same cycle as the second clock signal based on the frequency division ratio and the first clock signal.
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