公开(公告)号：US20240312981A1

公开(公告)日：2024-09-19

申请号：US18671451

申请日：2024-05-22

Applicant: Socionext Inc.

Inventor： Yoshito UCHIHASHI ,  Masahiro GION ,  Toshihiro NAKAMURA

IPC: H01L27/02

CPC classification number: H01L27/0285

Abstract: An ESD protection circuit includes: a protective element placed between VDD and VSS; an RC circuit; and an inverter connected to a node of the RC circuit at its input and to a node of the protective element at its output. The inverter includes a PMOS connected to VDD at its source and an NMOS connected to VSS at its source. The PMOS and the NMOS are connected in common to the node of the RC circuit at their gates and to the node of the protective element at their drains. The gate length of the PMOS is smaller than the gate length of the NMOS.