公开(公告)号：US20240312981A1

公开(公告)日：2024-09-19

申请号：US18671451

申请日：2024-05-22

Applicant: Socionext Inc.

Inventor： Yoshito UCHIHASHI ,  Masahiro GION ,  Toshihiro NAKAMURA

IPC: H01L27/02

CPC classification number: H01L27/0285

Abstract: An ESD protection circuit includes: a protective element placed between VDD and VSS; an RC circuit; and an inverter connected to a node of the RC circuit at its input and to a node of the protective element at its output. The inverter includes a PMOS connected to VDD at its source and an NMOS connected to VSS at its source. The PMOS and the NMOS are connected in common to the node of the RC circuit at their gates and to the node of the protective element at their drains. The gate length of the PMOS is smaller than the gate length of the NMOS.

公开(公告)号：US20240096870A1

公开(公告)日：2024-03-21

申请号：US18526546

申请日：2023-12-01

Applicant: Socionext Inc.

Inventor： Toshihiro NAKAMURA

IPC: H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0248 ,  H01L23/5286

Abstract: In a semiconductor integrated circuit device, a first power line extends in an X direction in an IO region and is formed in a first interconnect layer. A second power line extends in the X direction in a core region. A third power line extends in a Y direction, is formed in a second interconnect layer located below the first interconnect layer, and is connected to the first and second power lines. The third power line overlaps an external connection pad in planar view and is placed between adjacent interconnects in the X direction.

公开(公告)号：US20190051588A1

公开(公告)日：2019-02-14

申请号：US16165486

申请日：2018-10-19

Applicant: SOCIONEXT INC.

Inventor： Toshihiro NAKAMURA ,  Isao MOTEGI ,  Noriyuki SHIMAZU ,  Masanobu HIROSE ,  Taro FUKUNAGA

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

公开(公告)号：US20220254811A1

公开(公告)日：2022-08-11

申请号：US17730881

申请日：2022-04-27

Applicant: Socionext Inc.

Inventor： Masahisa IIDA ,  Toshihiro NAKAMURA

IPC: H01L27/118

Abstract: An IO cell includes a first output transistor and a second output transistor. A capacitance transistor is provided between external connection pads. The capacitance transistor is placed between the output transistors and an edge of the semiconductor integrated circuit device as viewed in plan. The gate length of the capacitance transistor is smaller than the gate length of the output transistors.

公开(公告)号：US20210028110A1

公开(公告)日：2021-01-28

申请号：US17071812

申请日：2020-10-15

Applicant: SOCIONEXT INC.

Inventor： Masanobu HIROSE ,  Toshihiro NAKAMURA

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/50

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects provided in I/O cell rows are connected to a power supply interconnect provided between the I/O cell rows via power supply interconnects. The power supply interconnect is thicker than the in-row power supply interconnects.

公开(公告)号：US20210233902A1

公开(公告)日：2021-07-29

申请号：US17233177

申请日：2021-04-16

Applicant: SOCIONEXT INC.

Inventor： Toshihiro NAKAMURA ,  Taro FUKUNAGA

IPC: H01L27/02 ,  H01L23/00 ,  H01L23/528

Abstract: A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.

公开(公告)号：US20220367442A1

公开(公告)日：2022-11-17

申请号：US17877534

申请日：2022-07-29

Applicant: Socionext Inc.

Inventor： Taro FUKUNAGA ,  Masahisa IIDA ,  Toshihiro NAKAMURA

IPC: H01L27/02

Abstract: In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.

公开(公告)号：US20190051601A1

公开(公告)日：2019-02-14

申请号：US16138868

申请日：2018-09-21

Applicant: SOCIONEXT INC.

Inventor： Masanobu HIROSE ,  Toshihiro NAKAMURA

IPC: H01L23/528 ,  H01L23/50 ,  H01L27/02

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects (21a to 21d) provided in I/O cell rows (10A, 10B) are connected to a power supply interconnect (23) provided between the I/O cell rows (10A, 10B) via power supply interconnects (25a to 25d). The power supply interconnect (23) is thicker than the in-row power supply interconnects (21a to 21d).