公开(公告)号：US6044850A

公开(公告)日：2000-04-04

申请号：US961242

申请日：1997-10-30

申请人： Soichiro Ozawa ,  Satoru Mihara ,  Kunihiko Nagase ,  Masaaki Aoyama ,  Naoki Nishida

发明人： Soichiro Ozawa ,  Satoru Mihara ,  Kunihiko Nagase ,  Masaaki Aoyama ,  Naoki Nishida

IPC分类号： C23F4/00 ,  H01L21/02 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/52 ,  B08B6/00

CPC分类号： H01L21/02071

摘要： Ashing process of a resist pattern used in a semiconductor device manufacturing method is conducted by exposing the resist, the wirings, and their peripheral regions to a first atmosphere which includes a first product obtained by plasmanizing a gas containing water at a rate of more than 30 flow rate %, and placing the resist in a second atmosphere which includes a second product obtained by plasmanizing an oxygen mixed gas which contains an oxygen gas as a principal component before or after or before and after the exposing step.

摘要翻译： 在半导体器件制造方法中使用的抗蚀剂图案的灰化处理通过将抗蚀剂，布线及其周边区域暴露于第一气氛来进行，该第一气氛包括通过使含有水的气体以大于30的比例等离子化而获得的第一产物 流量％，并将抗蚀剂置于第二气氛中，该第二气氛包括在暴露步骤之前或之后或之前或之后使包含氧气的氧气混合气体作为主要组分而得到的第二产物。

公开(公告)号：US20080176404A1

公开(公告)日：2008-07-24

申请号：US11907737

申请日：2007-10-17

申请人： Kunihiko Nagase ,  Akihiro Hasegawa

发明人： Kunihiko Nagase ,  Akihiro Hasegawa

IPC分类号： H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/31138 ,  H01L21/76808

摘要： The method for fabricating the semiconductor device comprises the step of forming an insulating film 14 having an opening 18; the step of forming an organic resist film 20a; the step of forming over the organic resist film 20a a mask film 20b having etching characteristics different from those of the organic resist film 20a; the step of forming an opening in the mask film 20b; and the step of etching the organic resist film 20a with the mask film 20b as the mask. In the step of etching the organic resist film, the organic resist film 20a is etched with a mixed gas of nitrogen gas and oxygen gas.

摘要翻译： 制造半导体器件的方法包括形成具有开口18的绝缘膜14的步骤; 形成有机抗蚀剂膜20a的步骤; 在有机抗蚀剂膜20上形成具有与有机抗蚀剂膜20a的蚀刻特性不同的蚀刻特性的掩模膜20b的步骤; 在掩模膜20b中形成开口的步骤; 以及用掩模膜20b作为掩模蚀刻有机抗蚀剂膜21a的步骤。 在蚀刻有机抗蚀剂膜的步骤中，用氮气和氧气的混合气体蚀刻有机抗蚀剂膜20a。

公开(公告)号：US6136723A

公开(公告)日：2000-10-24

申请号：US318613

申请日：1999-05-26

申请人： Kunihiko Nagase

发明人： Kunihiko Nagase

IPC分类号： H01L21/302 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/0276 ,  H01L21/76802

摘要： A method of fabricating a semiconductor device includes the steps of forming a resist pattern on a conductor layer, exposing the resist pattern to any of a plasma of a rare gas, a plasma of a mixture of a rare gas and a fluorine-containing gas, and a plasma of N.sub.2, and applying a dry etching process to the conductor layer while using the resist pattern as a mask.

摘要翻译： 制造半导体器件的方法包括以下步骤：在导体层上形成抗蚀剂图案，将抗蚀剂图案暴露于稀有气体的等离子体，稀有气体和含氟气体的混合物的等离子体中， 和N2的等离子体，并且在使用抗蚀剂图案作为掩模的同时对导体层进行干法蚀刻处理。

公开(公告)号：US20070111505A1

公开(公告)日：2007-05-17

申请号：US11356042

申请日：2006-02-17

申请人： Michio Oryoji ,  Kunihiko Nagase

发明人： Michio Oryoji ,  Kunihiko Nagase

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808

摘要： A semiconductor device manufacturing method forming an interconnection structure by a dual damascene process is disclosed that includes the steps of forming first and second interlayer insulating films successively over an interconnection layer, at least one of which includes a low dielectric constant material; forming a via hole through the first and second interlayer insulating films; filling the via hole with a burying material including an acid generator; causing an acid substance to be generated in the burying material; forming a chemically amplified resist film covering the second interlayer insulating film and the burying material; forming the pattern of an interconnection trench in the area including the via hole over the chemically amplified resist film; forming the interconnection trench by etching the second interlayer insulating film using the chemically amplified resist film as a mask; and filling the via hole and the interconnection trench with a conductive material.

摘要翻译： 公开了一种通过双镶嵌工艺形成互连结构的半导体器件制造方法，其包括在互连层上依次形成第一和第二层间绝缘膜的步骤，其中至少一个包括低介电常数材料; 通过所述第一和第二层间绝缘膜形成通孔; 用包括酸产生器的埋藏材料填充通孔; 导致在掩埋材料中产生酸性物质; 形成覆盖所述第二层间绝缘膜和所述掩埋材料的化学放大抗蚀剂膜; 在包括化学放大抗蚀剂膜上的通孔的区域中形成互连沟槽的图案; 通过使用化学放大抗蚀剂膜作为掩模蚀刻第二层间绝缘膜来形成互连沟槽; 并用导电材料填充通孔和互连沟槽。

公开(公告)号：US20060134909A1

公开(公告)日：2006-06-22

申请号：US10816959

申请日：2004-04-05

申请人： Kunihiko Nagase ,  Akihiro Hasegawa

发明人： Kunihiko Nagase ,  Akihiro Hasegawa

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/31138 ,  H01L21/76808

摘要： The method for fabricating the semiconductor device comprises the step of forming an insulating film 14 having an opening 18; the step of forming an organic resist film 20a; the step of forming over the organic resist film 20a a mask film 20b having etching characteristics different from those of the organic resist film 20a; the step of forming an opening in the mask film 20b; and the step of etching the organic resist film 20a with the mask film 20b as the mask. In the step of etching the organic resist film, the organic resist film 20a is etched with a mixed gas of nitrogen gas and oxygen gas.

摘要翻译： 制造半导体器件的方法包括形成具有开口18的绝缘膜14的步骤; 形成有机抗蚀剂膜20a的步骤; 在有机抗蚀剂膜20上形成具有与有机抗蚀剂膜20a的蚀刻特性不同的蚀刻特性的掩模膜20b的步骤; 在掩模膜20b中形成开口的步骤; 以及用掩模膜20b作为掩模蚀刻有机抗蚀剂膜21a的步骤。 在蚀刻有机抗蚀剂膜的步骤中，用氮气和氧气的混合气体蚀刻有机抗蚀剂膜20a。