公开(公告)号：US20040260746A1

公开(公告)日：2004-12-23

申请号：US10464882

申请日：2003-06-19

Applicant: International Business Machines Corporation ,  Sony Computer Entertainment Inc.

Inventor： Jeffrey Douglas Brown ,  Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Takeshi Yamazaki

IPC: G06F015/16

CPC classification number: G06F9/5011 ,  G06F2209/5014

Abstract: The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.

Abstract translation: 本发明在一个方面公开了一种微处理器。 在一个实施例中，微处理器包括被配置为使用带宽来处理应用的处理元件。 微处理器还包括一个接入整形器，它与处理元件相耦合，并配置成形成用于处理应用的存储请求。 在该实施例中，微处理器还包括耦合到接入整形器的带宽管理电路，并且被配置为基于请求跟踪带宽使用。 还公开了一种协调带宽分配的方法和处理器组件。

公开(公告)号：US20030229765A1

公开(公告)日：2003-12-11

申请号：US10371322

申请日：2003-02-21

Applicant: Sony Computer Entertainment Inc.

Inventor： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC: G06F012/00

CPC classification number: G06F12/1466 ,  H04L69/12

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

公开(公告)号：US20040243738A1

公开(公告)日：2004-12-02

申请号：US10448237

申请日：2003-05-29

Applicant: International Business Machines Corporation ,  Sony Computer Entertainment Inc.

Inventor： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

IPC: G06F013/28

CPC classification number: G06F13/28

Abstract: The present invention provides for asynchronous DMA command completion notification in a computer system. A command tag, associated with a plurality DMA command is generated. A DMA data movement command having the command tag is grouped with another DMA data movement command having the command tag. DMA commands belonging to the same tag group are monitored to see whether all DMA commands of the same tag group are completed.

Abstract translation: 本发明在计算机系统中提供异步DMA命令完成通知。 生成与多个DMA命令相关联的命令标签。 具有命令标签的DMA数据移动命令与具有命令标签的另一DMA数据移动命令分组。 监视属于同一标签组的DMA命令，以查看相同标签组的所有DMA命令是否完成。