公开(公告)号：US07528820B2

公开(公告)日：2009-05-05

申请号：US11172232

申请日：2005-06-29

申请人： Soo-Young Yoon ,  Yong-Ho Jang ,  Binn Kim ,  Soo-Hwan Moon

发明人： Soo-Young Yoon ,  Yong-Ho Jang ,  Binn Kim ,  Soo-Hwan Moon

IPC分类号： G09G3/36

CPC分类号： G11C19/28 ,  G11C19/00

摘要： A driving circuit for a flat panel display device includes shift register stages, each containing: a first TFT charging a Q node according to a start signal; a second TFT discharging the Q node according to an output voltage of a next shift register stage; a pull-up unit increasing an output voltage according to the Q node voltage; an odd pull-down unit decreasing the output voltage in an odd frame according to a QB-o node voltage; and an even pull-down unit decreasing the output voltage in an even frame according to a QB-e node voltage. A gate and drain of a third odd TFT connected to the QB-o node are connected to each other and receive an odd source voltage. A gate and drain of the third even TFT connected to the QB-e node are connected to each other and receive an even source voltage.

摘要翻译： 一种用于平板显示装置的驱动电路，包括移位寄存器级，每个移位寄存器级包含：根据起始信号对Q个节点充电的第一TFT; 第二TFT根据下一个移位寄存器级的输出电压对Q个节点进行放电; 上拉单元根据Q节点电压增加输出电压; 奇数下拉单元根据QB-o节点电压降低奇数帧中的输出电压; 以及均匀下拉单元根据QB-e节点电压降低偶数帧中的输出电压。 连接到QB-o节点的第三奇数TFT的栅极和漏极彼此连接并接收奇数源电压。 连接到QB-e节点的第三偶极TFT的栅极和漏极彼此连接并接收均匀的源极电压。

公开(公告)号：US20060139292A1

公开(公告)日：2006-06-29

申请号：US11172232

申请日：2005-06-29

申请人： Soo-Young Yoon ,  Yong-Ho Jang ,  Binn Kim ,  Soo-Hwan Moon

发明人： Soo-Young Yoon ,  Yong-Ho Jang ,  Binn Kim ,  Soo-Hwan Moon

IPC分类号： G09G3/36

CPC分类号： G11C19/28 ,  G11C19/00

摘要： A driving circuit for a flat panel display device includes shift register stages, each containing: a first TFT charging a Q node according to a start signal; a second TFT discharging the Q node according to an output voltage of a next shift register stage; a pull-up unit increasing an output voltage according to the Q node voltage; an odd pull-down unit decreasing the output voltage in an odd frame according to a QB-o node voltage; and an even pull-down unit decreasing the output voltage in an even frame according to a QB-e node voltage. A gate and drain of a third odd TFT connected to the QB-o node are connected to each other and receive an odd source voltage. A gate and drain of the third even TFT connected to the QB-e node are connected to each other and receive an even source voltage.

公开(公告)号：US07349519B2

公开(公告)日：2008-03-25

申请号：US11171562

申请日：2005-06-30

申请人： Yong-Ho Jang ,  Binn Kim ,  Soo-Young Yoon

发明人： Yong-Ho Jang ,  Binn Kim ,  Soo-Young Yoon

IPC分类号： G11C19/00

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G11C19/00 ,  G11C19/28

摘要： A shift register structure comprising a shift register for sequentially outputting voltages as a clock signal and a start voltage are inputted thereto, and a cleaner means connected to the shift register for removing noise within the start voltage. The cleaner means is a transistor for inputting a clock signal to a gate and for inputting a signal outputted from the shift register to a source.

摘要翻译： 输入移位寄存器结构，其包括用于顺序地输出电压作为时钟信号的移位寄存器和起始电压，以及连接到移位寄存器的清除器装置，用于消除起始电压内的噪声。 清洁装置是用于将时钟信号输入到门并将从移位寄存器输出的信号输入到源的晶体管。

公开(公告)号：US08049704B2

公开(公告)日：2011-11-01

申请号：US11173168

申请日：2005-06-30

申请人： Yong-Ho Jang ,  Binn Kim ,  Su-Hwan Moon ,  Nam-Wook Cho ,  Soo-Young Yoon

发明人： Yong-Ho Jang ,  Binn Kim ,  Su-Hwan Moon ,  Nam-Wook Cho ,  Soo-Young Yoon

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2310/0205 ,  G09G2310/0251 ,  G09G2310/08

摘要： A liquid crystal display (LCD) device comprises a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and data lines, each pixel region associated with a thin film transistor, a gate driving unit having an amorphous semiconductor and integrally formed with the liquid crystal panel capable of sending a scan signal to the gate lines having a pulse width longer than a turned on time of the thin film transistor located within the pixel region, and a data driving unit connected to the data lines capable of sending an image signal to the data lines.

摘要翻译： 液晶显示器（LCD）装置包括具有由多个栅极线和数据线限定的多个像素区域的液晶面板，与薄膜晶体管相关联的每个像素区域，具有非晶半导体的栅极驱动单元和一体的 形成有能够向位于像素区域内的薄膜晶体管的导通时间长的脉冲宽度的栅极线发送扫描信号的液晶面板，以及连接到能够发送的数据线的数据驱动单元 到数据线的图像信号。

公开(公告)号：US20060146979A1

公开(公告)日：2006-07-06

申请号：US11171562

申请日：2005-06-30

申请人： Yong-Ho Jang ,  Binn Kim ,  Soo-Young Yoon

发明人： Yong-Ho Jang ,  Binn Kim ,  Soo-Young Yoon

IPC分类号： G11C19/00

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G11C19/00 ,  G11C19/28

摘要： A shift register structure comprising a shift register for sequentially outputting voltages as a clock signal and a start voltage are inputted thereto, and a cleaner means connected to the shift register for removing noise within the start voltage. The cleaner means is a transistor for inputting a clock signal to a gate and for inputting a signal outputted from the shift register to a source.

摘要翻译： 输入移位寄存器结构，其包括用于顺序地输出电压作为时钟信号的移位寄存器和起始电压，以及连接到移位寄存器的清除器装置，用于消除起始电压内的噪声。 清洁装置是用于将时钟信号输入到门并将从移位寄存器输出的信号输入到源的晶体管。

公开(公告)号：US20060145991A1

公开(公告)日：2006-07-06

申请号：US11173168

申请日：2005-06-30

申请人： Yong-Ho Jang ,  Binn Kim ,  Su-Hwan Moon ,  Nam-Wook Cho ,  Soo-Young Yoon

发明人： Yong-Ho Jang ,  Binn Kim ,  Su-Hwan Moon ,  Nam-Wook Cho ,  Soo-Young Yoon

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2310/0205 ,  G09G2310/0251 ,  G09G2310/08

摘要： A liquid crystal display (LCD) device comprises a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and data lines, each pixel region associated with a thin film transistor, a gate driving unit having an amorphous semiconductor and integrally formed with the liquid crystal panel capable of sending a scan signal to the gate lines having a pulse width longer than a turned on time of the thin film transistor located within the pixel region, and a data driving unit connected to the data lines capable of sending an image signal to the data lines.

摘要翻译： 液晶显示器（LCD）装置包括具有由多个栅极线和数据线限定的多个像素区域的液晶面板，与薄膜晶体管相关联的每个像素区域，具有非晶半导体的栅极驱动单元和一体的 形成有能够向位于像素区域内的薄膜晶体管的导通时间长的脉冲宽度的栅极线发送扫描信号的液晶面板，以及连接到能够发送的数据线的数据驱动单元 到数据线的图像信号。

公开(公告)号：US20050156859A1

公开(公告)日：2005-07-21

申请号：US11020184

申请日：2004-12-27

申请人： Yong-Ho Jang ,  Nam-Wook Cho ,  Soo-Young Yoon

发明人： Yong-Ho Jang ,  Nam-Wook Cho ,  Soo-Young Yoon

IPC分类号： G09G3/20 ,  G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3674 ,  G09G2300/08 ,  G09G2310/0267 ,  G11C19/00 ,  G11C19/184 ,  G11C19/28

摘要： A driving circuit for a flat panel display device includes first and second generation units generating m-phase circulation enable control clocks and n-phase circulation form generation clocks; and a plurality of shift register stages generating output signals by using the m-phase circulation enable control clocks and the n-phase circulation form generation clocks. Each shift register stage includes an input terminal receiving the m-phase circulation enable control clocks; first and second nodes outputting first and second signals, respectively, using the m-phase circulation enable control clocks; a first transistor connected to the first node and receiving the n-phase circulation form generation clocks; a second transistor connected to the second node and the first transistor; and an output terminal between the first and second transistors and outputting one of the output signals.

摘要翻译： 用于平板显示装置的驱动电路包括产生m相循环使能控制时钟和n相循环形式生成时钟的第一和第二产生单元; 以及多个移位寄存器级，通过使用m相循环使能控制时钟和n相循环形式生成时钟来产生输出信号。 每个移位寄存器级包括接收m相循环使能控制时钟的输入端; 第一和第二节点分别使用m相循环启用控制时钟输出第一和第二信号; 连接到第一节点并接收n相循环形式的第一晶体管生成时钟; 连接到第二节点和第一晶体管的第二晶体管; 以及第一和第二晶体管之间的输出端子，并输出输出信号之一。

公开(公告)号：US07446748B2

公开(公告)日：2008-11-04

申请号：US11020184

申请日：2004-12-27

申请人： Yong-Ho Jang ,  Nam-Wook Cho ,  Soo-Young Yoon

发明人： Yong-Ho Jang ,  Nam-Wook Cho ,  Soo-Young Yoon

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3674 ,  G09G2300/08 ,  G09G2310/0267 ,  G11C19/00 ,  G11C19/184 ,  G11C19/28

摘要： A driving circuit for a flat panel display device includes first and second generation units generating m-phase circulation enable control clocks and n-phase circulation form generation clocks; and a plurality of shift register stages generating output signals by using the m-phase circulation enable control clocks and the n-phase circulation form generation clocks. Each shift register stage includes an input terminal receiving the m-phase circulation enable control clocks; first and second nodes outputting first and second signals, respectively, using the m-phase circulation enable control clocks; a first transistor connected to the first node and receiving the n-phase circulation form generation clocks; a second transistor connected to the second node and the first transistor; and an output terminal between the first and second transistors and outputting one of the output signals.

摘要翻译： 用于平板显示装置的驱动电路包括产生m相循环使能控制时钟和n相循环形式生成时钟的第一和第二产生单元; 以及多个移位寄存器级，通过使用m相循环使能控制时钟和n相循环形式生成时钟来产生输出信号。 每个移位寄存器级包括接收m相循环使能控制时钟的输入端; 第一和第二节点分别使用m相循环启用控制时钟输出第一和第二信号; 连接到第一节点并接收n相循环形式的第一晶体管生成时钟; 连接到第二节点和第一晶体管的第二晶体管; 以及第一和第二晶体管之间的输出端子，并输出输出信号之一。

公开(公告)号：US08581825B2

公开(公告)日：2013-11-12

申请号：US13223875

申请日：2011-09-01

申请人： Yong-Ho Jang ,  Soo-Young Yoon ,  Nam-Wook Cho

发明人： Yong-Ho Jang ,  Soo-Young Yoon ,  Nam-Wook Cho

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/06 ,  G11C19/184

摘要： A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.

摘要翻译： 用于平板显示装置的驱动电路包括用于产生n相形式产生时钟的生成单元; 以及多个移位寄存器级，用于使用n相形式产生时钟向多条栅极线顺序产生多个栅极信号，移位寄存器级中的一个分别包括用于分别输出第一和第二开关信号的第一和第二输出端 使用前述移位寄存器级之一的输出信号和随后的移位寄存器级之一的输出信号; 连接到第一输出端的第一晶体管，用于接收n相形成时钟之一; 以及连接到第二输出端和第一晶体管的第二晶体管，其中每个栅极线连接到第一和第二晶体管之间的节点。

公开(公告)号：US08031158B2

公开(公告)日：2011-10-04

申请号：US11167192

申请日：2005-06-28

申请人： Yong-Ho Jang ,  Soo-Young Yoon ,  Nam-Wook Cho

发明人： Yong-Ho Jang ,  Soo-Young Yoon ,  Nam-Wook Cho

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/06 ,  G11C19/184

摘要： A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.

摘要翻译： 用于平板显示装置的驱动电路包括用于产生n相形式产生时钟的生成单元; 以及多个移位寄存器级，用于使用n相形式产生时钟向多条栅极线顺序产生多个栅极信号，移位寄存器级中的一个分别包括用于分别输出第一和第二开关信号的第一和第二输出端 使用前述移位寄存器级之一的输出信号和随后的移位寄存器级之一的输出信号; 连接到第一输出端的第一晶体管，用于接收n相形成时钟之一; 以及连接到第二输出端和第一晶体管的第二晶体管，其中每个栅极线连接到第一和第二晶体管之间的节点。