公开(公告)号：US5787479A

公开(公告)日：1998-07-28

申请号：US639576

申请日：1996-04-29

申请人： Romesh Mangho Jessani ,  Belliappa Manavattira Kuttanna ,  Soummya Mallick ,  Rajesh Bhikhubhai Patel

发明人： Romesh Mangho Jessani ,  Belliappa Manavattira Kuttanna ,  Soummya Mallick ,  Rajesh Bhikhubhai Patel

IPC分类号： G06F11/00 ,  G06F12/08 ,  G06F12/16

CPC分类号： G06F11/004 ,  G06F12/0859

摘要： A method and system for preventing information corruption in a cache memory due to a bus error which occurs during a cache linefill operation is disclosed. The cache memory includes multiple cache lines, and a tag is associated with each cache line. In accordance with the present disclosure, a tag associated with a cache line is validated before a linefill operation is performed on the cache line. In response to an occurrence of a bus error during the linefill operation, the tag associated with the cache line for which a linefill operation is performed, is invalidated such that the information within the cache line remains valid during a linefill operation unless a bus error occurs.

摘要翻译： 公开了一种用于防止由于在高速缓存行填充操作期间发生的总线错误而在高速缓冲存储器中的信息损坏的方法和系统。 高速缓冲存储器包括多个高速缓存线，并且标签与每个高速缓存线相关联。 根据本公开，在对高速缓存行执行行填充操作之前，与高速缓存行相关联的标签被验证。 响应于在线路填充操作期间发生总线错误，与执行线路填充操作的高速缓存行相关联的标签被无效，使得在行填充操作期间，高速缓存行内的信息保持有效，除非发生总线错误 。

公开(公告)号：US5764940A

公开(公告)日：1998-06-09

申请号：US757186

申请日：1996-11-27

申请人： Soummya Mallick ,  Rajesh Bhikhubhai Patel ,  Romesh Mangho Jessani

发明人： Soummya Mallick ,  Rajesh Bhikhubhai Patel ,  Romesh Mangho Jessani

IPC分类号： G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/3802

摘要： A processor and method of executing instructions within a processor are disclosed, which permit both a branch instruction and a target instruction of the branch instruction to be executed in response to a single instruction fetch. In accordance with an illustrative embodiment, the processor, which has an associated memory, simultaneously fetches a plurality of instructions from the memory. Branch instructions among the plurality of instructions are then detected. In response to a detection of a branch instruction among the plurality of instructions, a determination is made whether a target instruction to be executed in response to execution of the branch instruction is one of the plurality of instructions. In response to a determination that the target instruction is one of the plurality of instructions, the processor executes the target instruction without making an additional instruction fetch.

摘要翻译： 公开了一种在处理器内执行指令的处理器和方法，其允许响应于单个指令提取来执行转移指令的分支指令和目标指令。 根据说明性实施例，具有关联存储器的处理器同时从存储器中取出多个指令。 然后检测多个指令之间的分支指令。 响应于多个指令中的分支指令的检测，确定响应于分支指令的执行而执行的目标指令是否是多个指令之一。 响应于目标指令是多个指令之一的确定，处理器执行目标指令而不进行附加指令提取。

公开(公告)号：US5737751A

公开(公告)日：1998-04-07

申请号：US622254

申请日：1996-03-26

申请人： Rajesh Bhikhubhai Patel ,  Sung-Ho Park ,  Romesh Mangho Jessani ,  Belliappa Manavattira Kuttanna

发明人： Rajesh Bhikhubhai Patel ,  Sung-Ho Park ,  Romesh Mangho Jessani ,  Belliappa Manavattira Kuttanna

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0897

摘要： A data processing system having enhanced memory performance is provided. The data processing system comprises a processor that issues memory requests, a multilevel storage system including a first level cache, a second level cache, and a main memory connected to the processor in a memory hierarchy, and a memory controller. The memory controller retrieves a cache line from main memory, when a memory request for the cache line is received from the processor at the first level cache that causes a miss in both the first level cache and the second level cache. The memory controller loads the retrieved cache line in both the first level cache and the second level cache if the received memory request is a load request, and loads the retrieved cache line in only the first level cache and not the second level cache if the received memory request is a store request. The resultant reduction in reloads to the second level cache enhances memory performance by allowing immediate execution of subsequent memory requests to the second level cache and producing a higher hit rate as a result of the reduction in castouts from the second level cache.

摘要翻译： 提供了具有增强的存储器性能的数据处理系统。 数据处理系统包括发出存储器请求的处理器，包括第一级缓存，第二级高速缓存和连接到存储器层级中的处理器的主存储器的多级存储系统和存储器控制器。 当从第一级高速缓存处理器接收到高速缓存行的存储器请求时，存储器控制器从主存储器中检索高速缓存行，这导致在第一级高速缓存和第二级高速缓存中都存在缺失。 如果接收到的存储器请求是加载请求，则存储器控制器将检索到的高速缓存行加载到第一级高速缓存和第二级高速缓存中，并且将所检索的高速缓存行加载到仅第一级高速缓存中而不是第二级高速缓存 内存请求是一个存储请求。 通过允许将后续存储器请求立即执行到第二级高速缓存并且由于来自第二级高速缓存的丢弃的减少而产生更高的命中率，从而减少重新加载到第二级高速缓存来增强存储器性能。

公开(公告)号：US5737749A

公开(公告)日：1998-04-07

申请号：US651013

申请日：1996-05-20

申请人： Rajesh Bhikhubhai Patel ,  Romesh Mangho Jessani ,  Belliappa Manavattira Kuttana

发明人： Rajesh Bhikhubhai Patel ,  Romesh Mangho Jessani ,  Belliappa Manavattira Kuttana

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/00

CPC分类号： G06F12/128 ,  G06F12/0848

摘要： A microprocessor that dynamically shares cache capacity comprising a controller that determines if all ways for a congruence class of a requested instruction are valid in the instruction cache and if a replacement way for the congruence class of the requested instruction is valid in a data cache. A lookup for the instruction is performed in the cache tags for the instruction cache and the data cache. If a hit occurs in either cache, the instruction is retrieved. If a miss occurs for the instruction in both the instruction cache and the data cache, the controller loads the instruction into either the instruction cache, if the replacement way is valid in the data cache or at least one way for the congruence class of the requested instruction is not valid in the instruction cache, or the data cache, if the replacement way is not valid in the data cache and all ways for the congruence class of the requested instruction are valid in the instruction cache.

摘要翻译： 动态共享高速缓存容量的微处理器包括一个控制器，该控制器确定所请求指令的一致等级的所有方式是否在指令高速缓存中有效，并且所请求指令的同余类的替换方式在数据高速缓存中是否有效。 在指令高速缓存和数据高速缓存的高速缓存标签中执行指令的查找。 如果任一缓存中发生命中，则会检索该指令。 如果指令高速缓存和数据高速缓存中的指令出现小命令，则控制器将指令加载到指令高速缓存中，如果替换方式在数据高速缓存中有效或至少一种方式用于请求的同余类 指令在指令高速缓存或数据高速缓存中无效，如果替换方式在数据高速缓存中无效，则所请求指令的同余类的所有方式在指令高速缓存中均有效。

公开(公告)号：US5812812A

公开(公告)日：1998-09-22

申请号：US740911

申请日：1996-11-04

申请人： Muhammad Nural Afsar ,  Romesh Mangho Jessani ,  Soummya Mallick ,  Robert Greg McDonald ,  Mukesh Sharma

发明人： Muhammad Nural Afsar ,  Romesh Mangho Jessani ,  Soummya Mallick ,  Robert Greg McDonald ,  Mukesh Sharma

IPC分类号： G06F9/38

CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/384

摘要： A method and system of implementing an early data dependency resolution mechanism for a high-performance data processing system that utilizes out-of-order instruction issue is disclosed. In accordance with the present disclosure, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines, and each of these cache lines is capable of storing multiple instructions. The register-dependency cache contains an identical number of cache lines as in the instruction cache, and each of the cache lines within the register-dependency cache is capable of storing an identical number of register-dependency units as instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified utilizing an Instruction Dispatch Unit. Each of the identified register-dependency units is then translated to its respective instruction utilizing a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle.

摘要翻译： 公开了一种利用无序指令问题的高性能数据处理系统实现早期数据依赖解析机制的方法和系统。 根据本公开，提供了指令高速缓存和寄存器依赖性高速缓存。 指令高速缓存具有多个高速缓存行，并且这些高速缓存行中的每一条都能够存储多个指令。 寄存器依赖性高速缓存包含与指令高速缓存中相同数量的高速缓存行，并且寄存器相关高速缓存内的每个高速缓存线能够存储与每个高速缓存行中的指令相同数量的寄存器依赖单元 在指令缓存中。 在单个处理器周期中，从寄存器依赖性缓存中取出一组寄存器依赖单元。 使用指令调度单元来识别在寄存器依赖单元组内没有转发数据依赖性的所有寄存器依赖单元。 然后，使用所述指令高速缓存中的相应高速缓存行，将所识别的寄存器依赖单元中的每一个转换为其相应的指令。 所有翻译的指令都是在下一个处理器周期内发出的。

公开(公告)号：US5805916A

公开(公告)日：1998-09-08

申请号：US758017

申请日：1996-11-27

申请人： Soummya Mallick ,  Michael Putrino ,  Romesh Mangho Jessani

发明人： Soummya Mallick ,  Michael Putrino ,  Romesh Mangho Jessani

IPC分类号： G06F9/302 ,  G06F9/38

CPC分类号： G06F9/30014 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3875

摘要： The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction cache for storing instructions, each instruction being associated with a rename register, a sequencer unit for providing an instruction to the execution unit, and a data cache for providing data to the execution unit. In one version, the execution unit includes a first stage which generates an intermediate result from the data according to an instruction; a means for providing a first portion of the intermediate result to an intermediate register; a means for providing a second portion of the intermediate result to a rename register associated with the instruction; a means for passing the first portion from the intermediate register to a second stage of the execution unit; a means for passing the second portion from the rename register to the second stage of the execution unit; wherein the second stage of the execution unit operates on the first and second portions according to the instruction.

摘要翻译： 本发明涉及一种多级执行单元，用于在微处理器中执行指令，该微处理器具有用于存储执行结果的多个重命名寄存器，用于存储指令的指令高速缓存，每个指令与重命名寄存器相关联，定序器单元用于提供指令 以及用于向执行单元提供数据的数据高速缓存。 在一个版本中，执行单元包括根据指令从数据生成中间结果的第一阶段; 用于将中间结果的第一部分提供给中间寄存器的装置; 用于将中间结果的第二部分提供给与指令相关联的重命名寄存器的装置; 用于将第一部分从中间寄存器传递到执行单元的第二级的装置; 用于将第二部分从重命名寄存器传递到执行单元的第二级的装置; 其中执行单元的第二级根据该指令在第一和第二部分上操作。

公开(公告)号：US5872948A

公开(公告)日：1999-02-16

申请号：US616613

申请日：1996-03-15

申请人： Soummya Mallick ,  Rajesh Bikhubhai Patel ,  Romesh Mangho Jessani ,  Michael Putrino

发明人： Soummya Mallick ,  Rajesh Bikhubhai Patel ,  Romesh Mangho Jessani ,  Michael Putrino

IPC分类号： G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of the second instruction is subject to execution of the first instruction. In response to a determination that execution of the second instruction is subject to execution of the first instruction, the second instruction is selectively executed prior to the first instruction in response to a parameter of at least one of the first and second instructions. In one embodiment, the parameter is an execution latency parameter of the first and second instructions.

摘要翻译： 公开了用于执行指令的处理器和方法，其提取第一和第二指令，其中第一指令以程序顺序在第二指令之前。 确定第二指令的执行是否受到第一指令的执行。 响应于第二指令的执行被执行第一指令的确定，响应于第一和第二指令中的至少一个指令的参数在第一指令之前选择性地执行第二指令。 在一个实施例中，该参数是第一和第二指令的执行等待时间参数。

公开(公告)号：US5913054A

公开(公告)日：1999-06-15

申请号：US768059

申请日：1996-12-16

申请人： Soummya Mallick ,  Rajesh Bhikubhai Patel ,  Albert John Loper ,  Romesh Mangho Jessani

发明人： Soummya Mallick ,  Rajesh Bhikubhai Patel ,  Albert John Loper ,  Romesh Mangho Jessani

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/312 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/3816 ,  G06F9/3824

摘要： A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

摘要翻译： 描述处理多寄存器指令的处理器和方法。 处理器包括执行电路和一组寄存器，它们都能够存储数据字。 指定要写入寄存器组内的相应多个寄存器的多个数据字的多寄存器指令被发送到执行电路。 响应于接收到多寄存器指令，执行电路执行多寄存器指令，使得在单个寄存器指令期间，多个数据字中的至少两个数据字被写入多个寄存器中的至少两个对应的寄存器 处理器的周期。

公开(公告)号：US5870577A

公开(公告)日：1999-02-09

申请号：US758066

申请日：1996-11-27

申请人： Rajesh B. Patel ,  Soummya Mallick ,  Romesh Mangho Jessani

发明人： Rajesh B. Patel ,  Soummya Mallick ,  Romesh Mangho Jessani

IPC分类号： G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857

摘要： When the instruction dispatch unit detects two consecutive immediate instructions in the instruction queue directed to the same execution unit, it dispatches both during the same cycle, making use of both GPR ports for the two required GPR operands. Instruction path directing logic directs the first instruction to the execution decoder of the one execution unit during the first occurring cycle and latches the second instruction until a second occurring cycle. It also directs the first immediate operand of the first instruction to a first input of an execution block in the one execution unit during the first occurring cycle. An operand path directing logic directs the first GPR operand referred to by the first instruction to a second input of the execution block during the first occurring cycle and latches a second GPR operand referred to by the second instruction until the second occurring cycle. The instruction path directing logic directs the second instruction to the execution decoder during the second occurring cycle and directs the second immediate operand of the second instruction to the first input of the execution block during the second occurring cycle. The operand path directing logic directs the second GPR operand to the second input of the execution block during the second occurring cycle. In this manner, two instructions are dispatched in a single cycle from the instruction queue to one execution unit of the multiple execution unit parallel computer.

摘要翻译： 当指令调度单元检测到指向同一个执行单元的指令队列中的两个连续的立即指令时，它将在相同的周期内调度两个GPR端口两个所需的GPR操作数。 指令路径指令逻辑在第一次出现周期期间将第一指令指向一个执行单元的执行解码器，并将第二指令锁存到第二个发生周期。 它还在第一个发生周期中将第一指令的第一个立即操作数定向到一个执行单元中执行块的第一个输入。 操作数路径指令逻辑将第一指令引用的第一GPR操作数引导到执行块的第二个输入，并锁存第二指令引用的第二个GPR操作数直到第二个发生周期。 指令路径指令逻辑在第二发生周期期间将第二指令指引到执行解码器，并且在第二发生周期期间将第二指令的第二立即操作数引导到执行块的第一输入。 操作数路径定向逻辑在第二次发生周期期间将第二GPR操作数引导到执行块的第二个输入。 以这种方式，从指令队列到多个执行单元并行计算机的一个执行单元的单个周期中分派两个指令。

公开(公告)号：US07739469B2

公开(公告)日：2010-06-15

申请号：US11268827

申请日：2005-11-08

申请人： Romesh Mangho Jessani ,  Antonio Torrini ,  Robert Koelling ,  David Baker

发明人： Romesh Mangho Jessani ,  Antonio Torrini ,  Robert Koelling ,  David Baker

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/12

CPC分类号： G06F9/32 ,  G06F9/328

摘要： An instruction set is executed from Read Only Memory (ROM). When a current instruction in the instruction set corresponds to a reserved patch memory block of ROM, a Random Access Memory (RAM) index and a ROM return address are loaded into a memory map, and a program counter is set to a first reserved ROM address. After jumping the program counter to the first reserved ROM address, the program counter is jumped to RAM based on the RAM index to execute a patch code, which includes at least one instruction to set the program counter to a second reserved ROM address. When the program counter equals the second reserved ROM address, the ROM return address is retrieved. Then the instruction set is executed from ROM based on the ROM return address.

摘要翻译： 指令集由只读存储器（ROM）执行。 当指令集中的当前指令对应于ROM的保留补丁存储器块时，将随机存取存储器（RAM）索引和ROM返回地址加载到存储器映射中，并且将程序计数器设置为第一保留ROM地址 。 在将程序计数器跳转到第一保留ROM地址之后，根据RAM索引将程序计数器跳转到RAM，以执行补丁码，该补丁码包括将程序计数器设置为第二保留ROM地址的至少一个指令。 当程序计数器等于第二保留ROM地址时，检索ROM返回地址。 然后根据ROM返回地址从ROM执行指令集。