公开(公告)号：US11170863B2

公开(公告)日：2021-11-09

申请号：US16921879

申请日：2020-07-06

申请人： Southern University of Science and Technology

发明人： Guobiao Zhang ,  Yida Li ,  Xiaodong Xiang ,  Hongyu Yu ,  Yuejin Guo ,  Shengming Zhou ,  Guoxing Zhang ,  Guangzhao Liu ,  Mingtao Hu ,  Wang Zhang ,  Mei Shen

IPC分类号： G11C17/16 ,  G11C29/00 ,  G11C7/14 ,  G11C11/56 ,  G11C13/00 ,  G11C17/18

摘要： The present invention discloses a multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAMMB). It comprises a plurality of RRAM cells stacked above a semiconductor substrate. Each RRAM cell comprises a RRAM layer, which is switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed RRAMs have different resistances.

公开(公告)号：US11616030B2

公开(公告)日：2023-03-28

申请号：US17539040

申请日：2021-11-30

申请人： Southern University of Science and Technology

发明人： Guobiao Zhang ,  Hongyu Yu ,  Shengming Zhou ,  Yuejin Guo ,  Kai Chen ,  Yida Li ,  Jun Lan

IPC分类号： H01L23/64 ,  H01L21/48 ,  H01L21/683 ,  H01L23/538 ,  H01L49/02

摘要： A method for making a three-dimensional (3-D) module includes the steps of: A) forming a laminate of alternate ceramic tape layers and internal electrode layers on a substrate; B) etching said laminate to form first and second capacitor stacks at said first and second locations; C) firing said first and second capacitor stacks integrally; D) forming first and second pairs of external electrodes on said first and second capacitor stacks, respectively.

公开(公告)号：US11217542B2

公开(公告)日：2022-01-04

申请号：US16926606

申请日：2020-07-10

申请人： Southern University of Science and Technology

发明人： Guobiao Zhang ,  Hongyu Yu ,  Yuejin Guo ,  Shengming Zhou ,  Guoxing Zhang ,  Guangzhao Liu ,  Mingtao Hu ,  Wang Zhang

IPC分类号： H01L23/64 ,  H01L21/48 ,  H01L21/683 ,  H01L23/538 ,  H01L49/02

摘要： A three-dimensional (3-D) module with integrated passive components includes a plurality of vertically stacked sub-modules. Each sub-module comprises a device level comprising a high-k dielectric (e.g. ceramic) material and an interconnect level comprising a low-k dielectric (e.g. organic) material. The passive components in the device level are fired integrally, whereas the device level and the interconnect level are fired independently.