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1.发明授权公开(公告)号：US07191315B2
公开(公告)日：2007-03-13
申请号：US09874173
申请日：2001-06-04
IPC分类号： G06F9/00
CPC分类号： G06F9/30098
摘要： The present invention provides methods and memory structures for efficient tracking and recycling of physical register assignments. The disclosed methods and memory structures each provide an approach to reduce the size of the memory structures needed to track the usage of the physical registers and the recycling of these registers.
摘要翻译： 本发明提供用于有效跟踪和回收物理寄存器分配的方法和存储器结构。 所公开的方法和存储结构各自提供了减少跟踪物理寄存器的使用所需的存储器结构的大小以及这些寄存器的再循环的方法。
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2.发明授权公开(公告)号：US07055020B2
公开(公告)日：2006-05-30
申请号：US09881071
申请日：2001-06-13
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F9/3842
摘要： A method and apparatus is provided for restoring a free physical register list to its previous state without having to physically restore any data. The method and semiconductor device utilizes sets of pointers to manage physical register pointers in the physical register list. The physical register list is able to independently track physical registers for multiple threads of a multithreading microprocessor.
摘要翻译： 提供了一种方法和装置，用于将空闲物理寄存器列表恢复到其先前状态，而不必物理地恢复任何数据。 该方法和半导体器件利用指针集来管理物理寄存器列表中的物理寄存器指针。 物理寄存器列表能够独立地跟踪多线程微处理器的多个线程的物理寄存器。
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3.发明授权Storing results of producer instructions to facilitate consumer instruction dependency tracking 有权存储生产者指令的结果以便于消费者指令依赖跟踪公开(公告)号：US07237096B1
公开(公告)日：2007-06-26
申请号：US10818043
申请日：2004-04-05
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： If a consumer instruction specifies a 64 bit source register comprised of results provided by two 32 bit producer instructions, the number of dependencies that must be tracked per source register can be decreased by transforming one or more of the 32 bit producer instructions so that rather than simply storing its result in a 32 bit destination register, the transformed instruction stores its result into a 64 bit logical register along with another 32 bit value held in another 32 bit register.
摘要翻译： 如果消费者指令指定由两个32位生产者指令提供的结果组成的64位源寄存器，则可以通过转换一个或多个32位生产者指令来减少每个源寄存器必须跟踪的依赖关系的数量， 简单地将其结果存储在32位目标寄存器中，变换后的指令将其结果存储到64位逻辑寄存器以及另一个32位寄存器中保存的另一个32位值。
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公开(公告)号：US06587369B2
公开(公告)日：2003-07-01
申请号：US09852429
申请日：2001-05-09
IPC分类号： G11C1100
摘要： A memory cell is provided to store a speculative data value until either a later speculative data value is generated or until the stored speculative data is determined to be the desired data, e.g. no longer speculative. At such time, the invention allows the stored speculative data to quickly and easily be stored as permanent data and further speculative data values to be stored.
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5.发明授权Superscalar processor having content addressable memory structures for determining dependencies 有权超标量处理器具有用于确定依赖性的内容可寻址存储器结构公开(公告)号：US06862676B1
公开(公告)日：2005-03-01
申请号：US09761494
申请日：2001-01-16
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.
摘要翻译： 呈现具有发送第一和第二输出信号的内容可寻址存储器结构的超标量处理器。 超标量处理器对指令集执行无序处理。 从第一输出信号，可以确定指令集当前获取的指令与先前的飞行中指令之间的依赖关系，并用于为所有飞行中的指令生成依赖矩阵。 从第二输出信号可以确定一旦取消了相关性就执行指令所需的数据的物理寄存器地址。
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6.发明授权System and method for accessing a memory array which tolerates non-exclusive read select enables 有权用于访问允许非排他读取选择的存储器阵列的系统和方法使能公开(公告)号：US06594184B2
公开(公告)日：2003-07-15
申请号：US09948180
申请日：2001-09-06
IPC分类号： G11C700
摘要： A memory array includes a plurality of memory cells logically arranged in M rows and N columns, wherein N is the number of memory cells per word of digital information and M is the number of words within the array. A plurality of N data output lines are associated with each of the N columns of the array for selectively retrieving output data from a word located at a predetermined word address in the array. Each data output line is selectively shared by each of the M memory cells within its associated column. Each of the cell output lines of the M memory cells in each of the N columns are logically OR-ed together to provide the output data retrieved by each data output line associated with each of the N columns.
摘要翻译： 存储器阵列包括逻辑上排列成M行和N列的多个存储器单元，其中N是数字信息每个字的存储器单元的数量，M是阵列内的字数。 多个N个数据输出线与阵列的N列中的每一个相关联，用于从位于阵列中的预定字地址的字选择性地检索输出数据。 每个数据输出线由其相关联的列中的每个M个存储器单元选择性共享。 N列中的每一个中的M个存储器单元的单元输出行的每个单元输出行一起被逻辑或并行，以提供与每个N列相关联的每个数据输出行检索的输出数据。
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