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    Secured phase-change devices
    1.
    发明授权
    Secured phase-change devices 有权
    安全相变装置

    公开(公告)号：US07085155B2

    公开(公告)日：2006-08-01

    申请号：US10775431

    申请日：2004-02-10

    申请人： Stanford R. Ovshinsky ,  Morrel H. Cohen

    发明人： Stanford R. Ovshinsky ,  Morrel H. Cohen

    IPC分类号： G11C11/00

    CPC分类号： G11C7/24 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0059 ,  G11C2213/75 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

    摘要： An electronic device for securing the contents of data storage and processing elements. The device includes a security element and a phase-change element connected in a parallel arrangement. The security element is a three-terminal device, having an ON state and an OFF state which differ in resistance and regulate electronic access to the phase-change element by controlling the flow of electrical current applied to the parallel combination. In the ON state, the resistance of the security element is less than that of the phase-change element, thereby precluding a determination of the resistance of the phase-change element. In this PROTECT mode, the contents of the phase-change element are secured. In the OFF state, the resistance of the security element is greater than that of the phase-change material so that the resistance of the parallel combination approaches that of the phase-change element. In this READ mode, the resistance and information content of the phase-change element can be determined.

    摘要翻译： 一种用于保护数据存储和处理元件的内容的电子设备。 该装置包括以并联装置连接的安全元件和相变元件。 安全元件是具有导通状态和断开状态的三端子器件，其通过控制施加到并联组合的电流的流动而不同于电阻并且调节对相变元件的电子访问。 在ON状态下，安全元件的电阻小于相变元件的电阻，从而阻止了相变元件的电阻的确定。 在该PROTECT模式下，确保相变元件的内容。 在OFF状态下，安全元件的电阻大于相变材料的电阻，使得并联组合的电阻接近相变元件的电阻。 在该READ模式中，可以确定相变元件的电阻和信息内容。

    Error reduction circuit for chalcogenide devices
    2.
    发明授权
    Error reduction circuit for chalcogenide devices 有权
    硫属化物装置的误差减少电路

    公开(公告)号：US07186999B2

    公开(公告)日：2007-03-06

    申请号：US11064637

    申请日：2005-02-24

    申请人： Stanford R. Ovshinsky ,  Morrel H. Cohen

    发明人： Stanford R. Ovshinsky ,  Morrel H. Cohen

    IPC分类号： H01L29/06

    CPC分类号： G11C13/0004

    摘要： An error reduction circuit for use in arrays of chalcogenide memory and computing devices. The error reduction circuit reduces the error associated with the output response of chalcogenide devices. In a preferred embodiment, the output response is resistance and the error reduction circuit reduces errors or fluctuations in the resistance. The error reduction circuit includes a network of chalcogenide devices, each of which is nominally equivalent and each of which is programmed into the same state having the same nominal resistance. The inclusion of multiple devices in the network of the instant error reduction circuit provides for a reduction in the contributions of both dynamic fluctuations and manufacturing fluctuations to the error in the output response.

    摘要翻译： 用于硫族化物存储器和计算设备阵列的误差减少电路。 误差降低电路减少与硫族化物器件的输出响应相关的误差。 在优选实施例中，输出响应是电阻，并且误差减小电路减小电阻的误差或波动。 误差减小电路包括一个硫族化物器件网络，其中每个器件名义上是等效的，并且每个都被编程成具有相同标称电阻的相同状态。 在瞬时误差减少电路的网络中包含多个设备提供了动态波动和制造波动对输出响应误差的贡献的降低。