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公开(公告)号:US5122996A
公开(公告)日:1992-06-16
申请号:US564512
申请日:1990-08-09
CPC分类号: G01R35/002 , G04F10/10
摘要: A method and apparatus performs time-interval to voltage conversion immediately and continuously allowing timing variations to be viewed and correlated with other voltage signals displayed on an oscilloscope. A calibration output assists in calibrating the vertical gain and offset of the oscilloscope. An automatic setup software routine finds suitable resolution and offset settings. The method includes the steps of selecting the type of time-interval to be measured, scaling the counting of a clock signal appropriately, offsetting the counting means as desired, counting the number of clock signals that occur during every selected time-interval, limiting the counted results to a preselected range, and converting the counted results to an analog voltage for display by an oscilloscope. And, in a preferred version of the method, when counted results are limited the operator is notified, and there is an additional step of detecting when time-intervals are occurring faster than they can be counted and notifying the operator of that too. A corresponding apparatus for performing the method is disclosed.
摘要翻译: 一种方法和装置立即执行电压转换的时间间隔并且连续地允许观看定时变化并与示波器上显示的其它电压信号相关联。 校准输出有助于校准示波器的垂直增益和偏移量。 自动设置软件例程找到合适的分辨率和偏移设置。 该方法包括以下步骤:选择要测量的时间间隔的类型,适当地缩放时钟信号的计数,根据需要偏移计数装置,对在每个选择的时间间隔期间发生的时钟信号的数量进行计数,限制 将结果计数到预选范围,并将计数结果转换为示波器显示的模拟电压。 而且,在该方法的优选版本中,当计数结果被限制时,通知操作者,并且还有一个额外的步骤来检测时间间隔发生的速度比它们可以被计数得更快,并通知操作者。 公开了一种用于执行该方法的相应设备。
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公开(公告)号:US5204678A
公开(公告)日:1993-04-20
申请号:US834190
申请日:1992-02-10
申请人: Clark P. Foley
发明人: Clark P. Foley
CPC分类号: G04F10/005
摘要: A dual-ranked time-interval conversion circuit. Two time trap circuits are employed to convert the time interval between a logic level transition of a first signal and a logic level transition of a second signal to an analog or digital signal representative of that time interval. Each time trap circuit employs a delay line for receiving and propagating the first signal and a series of taps and respective storage elements along the delay line for detecting and storing the logic level of the delay line at each tap at the time of receipt of a second signal. A first time trap circuit is employed to measure the time interval in course quanta of time and a second time trap circuit is employed to measure in fine quanta of time the time difference between the actual first signal-to-second signal time interval and the coarse measurement of that interval. A nulling circuit is provided for applying a delayed strobe signal to the second time trap circuit within a predetermined period of time following receipt of the first signal. This time is preferably equal to two coarse time quanta to allow for quantizing error. Delay circuits are provided to compensate for signal propagation delay through circuit devices. The outputs of the first and second time trap circuits are applied to a digital-to-analog conversion circuit or to a digital decoding circuit for producing an analog or digital output, respectively.
摘要翻译: 双排序时间间隔转换电路。 采用两个时间陷阱电路来将第一信号的逻辑电平转换和第二信号的逻辑电平转换之间的时间间隔转换为表示该时间间隔的模拟或数字信号。 每个陷阱电路采用延迟线,用于沿着延迟线接收和传播第一信号和一系列抽头和相应的存储元件,用于在接收到第二信号时检测并存储每个抽头处的每个抽头处的延迟线的逻辑电平 信号。 采用第一次陷波电路来测量时间的时间间隔,并且采用第二时间陷波电路以精确的时间量测量实际的第一信号与第二信号时间间隔与粗略的时间差之间的时间差 测量间隔。 提供归零电路用于在接收到第一信号之后的预定时间段内将延迟的选通信号施加到第二时间陷波电路。 这个时间优选等于两个粗时间量子以允许量化误差。 提供延迟电路以补偿通过电路器件的信号传播延迟。 第一和第二时间陷波电路的输出分别被施加到数模转换电路或数字解码电路,以产生模拟或数字输出。
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公开(公告)号:US4985844A
公开(公告)日:1991-01-15
申请号:US348434
申请日:1989-05-08
申请人: Clark P. Foley , Donald L. Taylor
发明人: Clark P. Foley , Donald L. Taylor
IPC分类号: G06F17/18
CPC分类号: G06F17/18
摘要: A method for producing a statistical profile of a repetitive electrical signal entails selecting a window pulse width that is preferably a large multiple of the period of the signal, setting a comparison threshold, and counting the time that the signal is above (or below) the comparison threshold during the window pulse. The comparison threshold is then repeatedly incremented (or decremented) over the amplitude range of the signal, while this procedure is repeated at each level. The difference is then taken between the times measured at adjacent amplitude increments and the absolute value of these differences is displayed as the waveform profile. An apparatus for implementing this method includes a counter/timer, a gate, a comparator, a pulse generation circuit, a comparison threshold generation circuit, and a microprocessor for controlling the other circuit elements and performing calculations. The incoming repetitive signal is coupled to one input of the comparator and the output of the comparison threshold generation circuit is coupled to the other input. The output of the comparator is applied to the gate input along with the output of the pulse generation circuit. The output of the gate enables the counter/timer. The microprocessor controls the comparison threshold generation circuit and the pulse generation circuit, reads back the output of the counter/timer, and calculates the absolute value of the differences between times counted at adjacent amplitude thresholds.
摘要翻译: 用于产生重复电信号的统计特征的方法需要选择窗口脉冲宽度,该窗口脉冲宽度优选地是信号周期的大倍数,设置比较阈值,以及对信号高于(或更低)的时间进行计数 窗口脉冲期间的比较阈值。 然后,比较阈值在信号的振幅范围内重复增加(或递减),同时在每个级别重复此过程。 然后在相邻振幅增量测量的时间之间取差值,并将这些差值的绝对值显示为波形曲线。 用于实现该方法的装置包括计数器/定时器,门,比较器,脉冲发生电路,比较阈值生成电路和用于控制其他电路元件并执行计算的微处理器。 输入的重复信号耦合到比较器的一个输入,并且比较阈值产生电路的输出耦合到另一个输入端。 比较器的输出与脉冲发生电路的输出一起施加到栅极输入。 门的输出使能计数器/定时器。 微处理器控制比较阈值生成电路和脉冲发生电路,读出计数器/定时器的输出,并计算相邻振幅阈值计数的时间差的绝对值。
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