-
1.发明授权Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition 有权基于检测失速条件在多线程处理器内执行线程切换操作的方法和系统公开(公告)号：US06850961B2
公开(公告)日：2005-02-01
申请号：US10251583
申请日：2002-09-20
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A stall condition relating to the first thread within a processor pipeline of the multithreaded processor is detected. The elapsing of a predetermined time interval subsequent to the detection of the stall condition is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread and the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.
摘要翻译： 一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。 检测与多线程处理器的处理器流水线内的第一线程有关的失速状态。 也检测到在停止状态的检测之后的预定时间间隔的经过。 响应于检测第一线程的第一预定量指令信息的调度和预定时间间隔的经过，对指令流缓冲器的输出进行线程切换操作。
-
2.发明授权Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instruction 有权基于检测到分支指令，在多线程处理器内执行线程切换操作的方法和系统公开(公告)号：US06795845B2
公开(公告)日：2004-09-21
申请号：US10251204
申请日：2002-09-20
IPC分类号： G06F900
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A branch instruction within the instruction information of the first thread to be dispatched from the instruction information source is also detected. Responsive to the detection of the branch instruction and the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
摘要翻译： 一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。 还检测从指令信息源发送的第一线程的指令信息内的分支指令。 响应于分支指令的检测和对第一线程的第一预定量指令信息的调度的检测，针对指令流缓冲器的输出执行线程切换操作。 因此开始从指令流缓存器发送第二线程的指令信息。
-
3.发明授权Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a thread 有权在多线程处理器内执行线程切换操作的方法和系统，该方法和系统基于检测到一条线程的指令信息流不存在公开(公告)号：US06785890B2
公开(公告)日：2004-08-31
申请号：US10251527
申请日：2002-09-20
IPC分类号： G06F1500
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. An absence of a flow of instruction information of the first thread into the instruction information source from an upstream source in a processor pipeline is detected. The elapsing of a predetermined time interval subsequent to the detection of the absence of the flow of the instruction information is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.
摘要翻译： 一种在多线程处理器内执行线程切换操作的方法包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。 检测到来自处理器管线中的上游源的第一线程的指令信息流不存在于指令信息源中。 还检测到在检测到指令信息的流动之后的预定时间间隔的经过。 响应于检测第一线程的第一预定量指令信息的调度，并且响应于预定时间间隔的经过，针对指令流缓冲器的输出执行线程切换操作。 因此开始从指令流缓存器发送第二线程的指令信息。
-
4.发明授权Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor 有权将流标记插入到指令流中以指示多线程处理器内的线程切换操作的方法和系统公开(公告)号：US06865740B2
公开(公告)日：2005-03-08
申请号：US10248000
申请日：2002-09-20
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. A flow marker is inserted into an instruction stream, the instruction stream including the instruction information of the first thread dispatched from the instruction information source, and the flow marker indicating that the thread switching operation has occurred. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.
摘要翻译： 一种在多线程处理器内执行线程切换操作的方法包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。 响应于检测第一线程的第一预定量指令信息的调度，针对指令流缓冲器的输出执行线程切换操作。 流标记被插入到指令流中，指令流包括从指令信息源调度的第一线程的指令信息和指示线程切换操作已经发生的流标记。 因此开始从指令流缓存器发送第二线程的指令信息。
-
5.发明授权Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction 失效在多线程处理器内执行线程切换操作的方法和系统，该方法和系统基于用于完整指令的指令信息量的分派公开(公告)号：US06971104B2
公开(公告)日：2005-11-29
申请号：US10251508
申请日：2002-09-20
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.
摘要翻译： 一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。 响应于对第一线程的第一预定量的指令信息的调度的检测，针对指令流缓冲器的输出执行线程切换操作。 因此开始从指令流缓存器发送第二线程的指令信息。 指令信息的预定量可以等于或大于用于第一指令集的完整指令的指令信息的最小量。
-
6.发明授权Method and system to perform a thread switching operation within a multithreaded processor based on detection of a flow marker within an instruction information 有权基于在指令信息内的流标记的检测来执行多线程处理器内的线程切换操作的方法和系统公开(公告)号：US06854118B2
公开(公告)日：2005-02-08
申请号：US10251599
申请日：2002-09-20
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A flow marker within instruction information for the first thread received at the instruction information source is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the detection of the flow marker, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.
摘要翻译： 一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。 还检测在指令信息源处接收到的第一线程的指令信息内的流标记。 响应于检测第一线程的第一预定量的指令信息的调度，并且响应于流标记的检测，针对指令流缓冲器的输出执行线程切换操作。 因此开始从指令流缓存器发送第二线程的指令信息。
-
7.发明授权公开(公告)号：US06981261B2
公开(公告)日：2005-12-27
申请号：US10251542
申请日：2002-09-20
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.
摘要翻译： 一种在多线程处理器内执行线程切换操作的方法。 检测第一线程从指令流缓存器到多线程处理器内的指令预解码器的第一预定量的指令信息的调度。 响应于对第一线程的第一预定量的指令信息的调度的检测，针对指令流缓冲器的输出执行线程切换操作。 因此开始从指令流缓存器发送第二线程的指令信息。 处理器资源的使用根据针对已处理（或调度处理）的特定线程的指令数据量而不是根据任意的定时机制分配在线程之间。
-
8.发明授权公开(公告)号：US06535905B1
公开(公告)日：2003-03-18
申请号：US09302633
申请日：1999-04-29
IPC分类号： G06F900
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.
摘要翻译： 一种在多线程处理器内执行线程切换操作的方法。 检测第一线程从指令流缓存器到多线程处理器内的指令预解码器的第一预定量的指令信息的调度。 响应于对第一线程的第一预定量的指令信息的调度的检测，针对指令流缓冲器的输出执行线程切换操作。 因此开始从指令流缓存器发送第二线程的指令信息。 处理器资源的利用根据针对已处理（或调度处理）的特定线程的指令数据量而不是根据任意的定时机制分配在线程之间。
-
9.发明授权System and method of maintaining and utilizing multiple return stack buffers 失效维护和利用多个返回堆栈缓冲区的系统和方法公开(公告)号：US06374350B1
公开(公告)日：2002-04-16
申请号：US09584890
申请日：2000-06-01
IPC分类号： G06F942
CPC分类号： G06F9/3806 , G06F9/30054
摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.
摘要翻译： 提供微处理器中的指令流水线。 指令流水线包括多个流水线单元，多个流水线单元中的每一个处理多个指令。 多个流水线单元中的至少两个是流水线的至少一些指令的源。 该流水线还包括至少两个推测返回地址堆栈，每个耦合的推测返回地址栈耦合到至少一个指令源单元。 每个推测返回地址堆栈都能够存储至少两个推测返回地址。
-
公开(公告)号：US6151671A
公开(公告)日：2000-11-21
申请号：US27407
申请日：1998-02-20
CPC分类号： G06F9/3806 , G06F9/30054
摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.02 秒)