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公开(公告)号：US20100211738A1
公开(公告)日：2010-08-19
申请号：US12733338
申请日：2008-08-26
IPC分类号： G06F12/00
CPC分类号： G06F3/0658 , G06F3/0608 , G06F3/0656 , G06F3/0689
摘要： The present invention relates to a mass storage system with improved usage of buffer capacity, and more specifically to a mass storage system for real-time data storage with an embedded controller. According to the invention, the mass storage system has a first data path between a real-time data interface and a mass storage array, the first data path including a data buffer without access latency, and a second data path between an embedded processor and the mass storage array, wherein the data buffer without access latency is also used as a data buffer for non real-time data transfers between the embedded processor and the mass storage array.
摘要翻译： 本发明涉及具有改进的缓冲器容量使用的大容量存储系统，更具体地涉及一种用于利用嵌入式控制器实时数据存储的海量存储系统。 根据本发明，大容量存储系统具有实时数据接口和大容量存储阵列之间的第一数据路径，第一数据路径包括无访问延迟的数据缓冲器，以及嵌入式处理器与第二数据路径之间的第二数据路径 大容量存储阵列，其中没有访问延迟的数据缓冲器也用作用于嵌入式处理器和大容量存储阵列之间的非实时数据传输的数据缓冲器。
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公开(公告)号：US08285932B2
公开(公告)日：2012-10-09
申请号：US12733338
申请日：2008-08-26
IPC分类号： G06F12/00
CPC分类号： G06F3/0658 , G06F3/0608 , G06F3/0656 , G06F3/0689
摘要： The present invention relates to a mass storage system with improved usage of buffer capacity, and more specifically to a mass storage system for real-time data storage with an embedded controller. According to the invention, the mass storage system has a first data path between a real-time data interface and a mass storage array, the first data path including a data buffer without access latency, and a second data path between an embedded processor and the mass storage array, wherein the data buffer without access latency is also used as a data buffer for non real-time data transfers between the embedded processor and the mass storage array.
摘要翻译： 本发明涉及具有改进的缓冲器容量使用的大容量存储系统，更具体地涉及一种用于利用嵌入式控制器实时数据存储的海量存储系统。 根据本发明，大容量存储系统具有实时数据接口和大容量存储阵列之间的第一数据路径，第一数据路径包括无访问延迟的数据缓冲器，以及嵌入式处理器与第二数据路径之间的第二数据路径 大容量存储阵列，其中没有访问延迟的数据缓冲器也用作用于嵌入式处理器和大容量存储阵列之间的非实时数据传输的数据缓冲器。
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公开(公告)号：US08234448B2
公开(公告)日：2012-07-31
申请号：US12733292
申请日：2008-08-05
IPC分类号： G06F12/16
CPC分类号： G06F11/1088 , G06F11/1076 , G06F2211/1016 , H04N21/2182 , H04N21/2318
摘要： The present invention relates to a redundancy protected mass storage system with increased performance, and more specifically to a mass storage system with multiple storage units. According to the invention, the resources that are essentially provided for compensating the damage of one or more storage units are also used to enhance the system performance. For this purpose during reading or writing the storage system just waits for the responses of a minimum number of required storage units to start reading or writing, respectively.
摘要翻译： 本发明涉及具有增强性能的冗余保护大容量存储系统，更具体地说涉及具有多个存储单元的大容量存储系统。 根据本发明，基本上提供用于补偿一个或多个存储单元的损坏的资源也用于增强系统性能。 为此，在读取或写入存储系统时，只需等待最少数量的所需存储单元的响应即可开始读取或写入。
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公开(公告)号：US20110055472A1
公开(公告)日：2011-03-03
申请号：US12733292
申请日：2008-08-05
IPC分类号： G06F12/08
CPC分类号： G06F11/1088 , G06F11/1076 , G06F2211/1016 , H04N21/2182 , H04N21/2318
摘要： The present invention relates to a redundancy protected mass storage system with increased performance, and more specifically to a mass storage system with multiple storage units. According to the invention, the resources that are essentially provided for compensating the damage of one or more storage units are also used to enhance the system performance. For this purpose during reading or writing the storage system just waits for the responses of a minimum number of required storage units to start reading or writing, respectively.
摘要翻译： 本发明涉及具有增强性能的冗余保护大容量存储系统，更具体地说涉及具有多个存储单元的大容量存储系统。 根据本发明，基本上提供用于补偿一个或多个存储单元的损坏的资源也用于增强系统性能。 为此，在读取或写入存储系统时，只需等待最少数量的所需存储单元的响应即可开始读取或写入。
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5.发明申请Method for storing files on a storage medium, storage medium, and video recording apparatus using the method 有权使用该方法在存储介质，存储介质和视频记录装置上存储文件的方法公开(公告)号：US20090059737A1
公开(公告)日：2009-03-05
申请号：US12231027
申请日：2008-08-28
申请人： Johann Maas , Axel Kochale , Stefan Abeling
发明人： Johann Maas , Axel Kochale , Stefan Abeling
CPC分类号： G11B20/1254 , G11B27/105 , G11B27/329 , G11B2020/1289 , G11B2220/2516
摘要： In a storage medium, an address space is defined which is divided into a first area and a second area. According to the invention, at least one file is stored on the medium which is split into small data packets and large data packets. All small data packets are stored on said first area, and all large data packets are stored on said second area. A single file allocation table (FAT) is used and is small by having one entry per data packet.
摘要翻译： 在存储介质中，定义了被分成第一区域和第二区域的地址空间。 根据本发明，至少一个文件被存储在被分割成小数据分组和大数据分组的介质上。 所有小数据分组被存储在所述第一区域上，并且所有大数据分组被存储在所述第二区域上。 使用单个文件分配表（FAT），并且通过每个数据分组具有一个条目而较小。
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6.发明授权Method for storing files on a storage medium, storage medium, and video recording apparatus using the method 有权使用该方法在存储介质，存储介质和视频记录装置上存储文件的方法公开(公告)号：US08074015B2
公开(公告)日：2011-12-06
申请号：US12231027
申请日：2008-08-28
申请人： Johann Maas , Axel Kochale , Stefan Abeling
发明人： Johann Maas , Axel Kochale , Stefan Abeling
IPC分类号： G06F12/00
CPC分类号： G11B20/1254 , G11B27/105 , G11B27/329 , G11B2020/1289 , G11B2220/2516
摘要： In a storage medium, an address space is defined which is divided into a first area and a second area. According to the invention, at least one file is stored on the medium which is split into small data packets and large data packets. All small data packets are stored on said first area, and all large data packets are stored on said second area. A single file allocation table (FAT) is used and is small by having one entry per data packet.
摘要翻译： 在存储介质中，定义了被分成第一区域和第二区域的地址空间。 根据本发明，至少一个文件被存储在被分割成小数据分组和大数据分组的介质上。 所有小数据分组被存储在所述第一区域上，并且所有大数据分组被存储在所述第二区域上。 使用单个文件分配表（FAT），并且通过每个数据分组具有一个条目而较小。
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公开(公告)号：US20130138875A1
公开(公告)日：2013-05-30
申请号：US13816250
申请日：2011-08-08
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F13/1684 , G06F2212/7202 , G06F2212/7203 , G06F2212/7208
摘要： High speed mass storage devices using NAND flash memories (MDY.X) are suitable for recording and playing back a video data stream under real-time conditions, wherein the data are handled page-wise in the flash memories and are written in parallel to multiple memory buses (MBy). However, for operating with multiple independent data streams a significant buffer size is required. According to the invention, data from different data streams are collected in corresponding different buffers (FIFO 1, . . . , FIFO Z) until the amount of collected data in a current buffer corresponds to a current one of the data blocks. Then, the data of the current data block from the current buffer are stored into memories connected to a current one of the memory buses, wherein the following buffered data block of the related data stream is later on stored into memories connected to a following one of the memory buses, the number of the following memory bus being increased with respect to the number of the current memory bus. These steps are repeated, also for the other ones of the data streams using other available ones of the buffers and other ones of the memory buses. In combination with a corresponding buffer control it is possible to allocate and use a minimum number of buffers in a flexible way.
摘要翻译： 使用NAND闪速存储器（MDY.X）的高速大容量存储装置适用于在实时条件下记录和重放视频数据流，其中数据在闪速存储器中被逐页地处理并被并行写入多个 内存总线（MBy）。 然而，对于使用多个独立数据流进行操作，需要显着的缓冲区大小。 根据本发明，来自不同数据流的数据被收集在相应的不同缓冲器（FIFO 1，...，FIFO Z）中，直到当前缓冲器中收集的数据量对应于当前数据块中的一个。 然后，将来自当前缓冲器的当前数据块的数据存储到连接到当前一个存储器总线的存储器中，其中相关数据流的后续缓冲数据块稍后被存储到连接到下一个存储器总线 存储器总线，相对于当前存储器总线的数量增加了以下存储器总线的数量。 重复这些步骤，对于使用缓冲器中的其他可用缓冲器和其它存储器总线的数据流中的其他步骤也是如此。 结合相应的缓冲区控制，可以以灵活的方式分配和使用最少数量的缓冲区。
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公开(公告)号：US09026722B2
公开(公告)日：2015-05-05
申请号：US13816250
申请日：2011-08-08
CPC分类号： G06F12/0246 , G06F13/1684 , G06F2212/7202 , G06F2212/7203 , G06F2212/7208
摘要： High speed mass storage devices using NAND flash memories (MDY.X) are suitable for recording and playing back a video data stream under real-time conditions, wherein the data are handled page-wise in the flash memories and are written in parallel to multiple memory buses (MBy). However, for operating with multiple independent data streams a significant buffer size is required. According to the invention, data from different data streams are collected in corresponding different buffers (FIFO 1, . . . , FIFO Z) until the amount of collected data in a current buffer corresponds to a current one of the data blocks. Then, the data of the current data block from the current buffer are stored into memories connected to a current one of the memory buses, wherein the following buffered data block of the related data stream is later on stored into memories connected to a following one of the memory buses, the number of the following memory bus being increased with respect to the number of the current memory bus. These steps are repeated, also for the other ones of the data streams using other available ones of the buffers and other ones of the memory buses. In combination with a corresponding buffer control it is possible to allocate and use a minimum number of buffers in a flexible way.
摘要翻译： 使用NAND闪速存储器（MDY.X）的高速大容量存储装置适用于在实时条件下记录和重放视频数据流，其中数据在闪速存储器中被逐页地处理并被并行写入多个 内存总线（MBy）。 然而，对于使用多个独立数据流进行操作，需要显着的缓冲区大小。 根据本发明，来自不同数据流的数据被收集在相应的不同缓冲器（FIFO 1，...，FIFO Z）中，直到当前缓冲器中收集的数据量对应于当前数据块中的一个。 然后，将来自当前缓冲器的当前数据块的数据存储到连接到当前一个存储器总线的存储器中，其中相关数据流的后续缓冲数据块稍后被存储到连接到下一个存储器总线 存储器总线，相对于当前存储器总线的数量增加了以下存储器总线的数量。 重复这些步骤，对于使用缓冲器中的其他可用缓冲器和其它存储器总线的数据流中的其他步骤也是如此。 结合相应的缓冲区控制，可以以灵活的方式分配和使用最少数量的缓冲区。
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公开(公告)号：US08933735B2
公开(公告)日：2015-01-13
申请号：US14232257
申请日：2012-07-12
申请人： Holger Kropp , Herbert Schuetze , Stefan Abeling
发明人： Holger Kropp , Herbert Schuetze , Stefan Abeling
IPC分类号： H03L7/06
CPC分类号： H03L7/22 , H03L7/0814
摘要： A clock generation circuit comprises an internal clock signal source providing an internal clock signal and a synchronization device for synchronization the internal clock signal with a reference clock signal provided externally from the clock generation circuit. The synchronization device comprises n delay locked loop circuits, n being an integer greater than 1, each delay locked loop circuit having a clock input for receiving the internal clock signal and a clock output for providing an output clock signal with an individual phase shift that is adjustable. The synchronization device further comprises a multiplexer having n inputs and an output wherein each of the n inputs is connected to an output of one of the n delay locked loops and a control circuit. The control circuit is adapted to adjust at least one of the delay locked loop circuits for providing an individual phase shift according to a current phase shift and to select that input of the multiplexer that receives an output clock signal of the adjusted delay locked loop circuit that is synchronized in frequency and phase with the reference clock signal, wherein the output of the multiplexer provides that output clock signal as synchronized clock signal, and wherein the control circuit is adapted to toggle between the n delay locked loop circuits, in a way that the phase of the internal clock signal is successively shifted according to the current phase shift between the internal clock signal and the reference clock signal.
摘要翻译： 时钟发生电路包括提供内部时钟信号的内部时钟信号源和用于使内部时钟信号与从时钟发生电路外部提供的参考时钟信号同步的同步装置。 同步装置包括n个延迟锁定环电路，n是大于1的整数，每个延迟锁定环电路具有用于接收内部时钟信号的时钟输入和用于提供输出时钟信号的时钟输出， 可调。 同步装置还包括具有n个输入和多个输出的多路复用器，其中n个输入中的每一个连接到n个延迟锁定环中的一个的输出和一个控制电路。 控制电路适于调整延迟锁定环电路中的至少一个，以根据当前相移提供单独的相移，并选择接收经调整的延迟锁定环电路的输出时钟信号的多路复用器的输入， 在频率和相位与参考时钟信号同步，其中多路复用器的输出将该输出时钟信号提供为同步的时钟信号，并且其中控制电路适于在n个延迟锁定环电路之间切换， 内部时钟信号的相位根据内部时钟信号和参考时钟信号之间的当前相移而相继移位。
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公开(公告)号：US20140145770A1
公开(公告)日：2014-05-29
申请号：US14232257
申请日：2012-07-12
申请人： Holger Kropp , Herbert Schuetze , Stefan Abeling
发明人： Holger Kropp , Herbert Schuetze , Stefan Abeling
IPC分类号： H03L7/22
CPC分类号： H03L7/22 , H03L7/0814
摘要： A clock generation circuit comprises an internal clock signal source providing an internal clock signal and a synchronization device for synchronization the internal clock signal with a reference clock signal provided externally from the clock generation circuit. The synchronization device comprises n delay locked loop circuits, n being an integer greater than 1, each delay locked loop circuit having a clock input for receiving the internal clock signal and a clock output for providing an output clock signal with an individual phase shift that is adjustable. The synchronization device further comprises a multiplexer having n inputs and an output wherein each of the n inputs is connected to an output of one of the n delay locked loops and a control circuit. The control circuit is adapted to adjust at least one of the delay locked loop circuits for providing an individual phase shift according to a current phase shift and to select that input of the multiplexer that receives an output clock signal of the adjusted delay locked loop circuit that is synchronized in frequency and phase with the reference clock signal, wherein the output of the multiplexer provides that output clock signal as synchronized clock signal, and wherein the control circuit is adapted to toggle between the n delay locked loop circuits, in a way that the phase of the internal clock signal is successively shifted according to the current phase shift between the internal clock signal and the reference clock signal.
摘要翻译： 时钟发生电路包括提供内部时钟信号的内部时钟信号源和用于使内部时钟信号与从时钟发生电路外部提供的参考时钟信号同步的同步装置。 同步装置包括n个延迟锁定环电路，n是大于1的整数，每个延迟锁定环电路具有用于接收内部时钟信号的时钟输入和用于提供输出时钟信号的时钟输出， 可调。 同步装置还包括具有n个输入和多个输出的多路复用器，其中n个输入中的每一个连接到n个延迟锁定环中的一个的输出和一个控制电路。 控制电路适于调整延迟锁定环电路中的至少一个，以根据当前相移提供单独的相移，并选择接收经调整的延迟锁定环电路的输出时钟信号的多路复用器的输入， 在频率和相位与参考时钟信号同步，其中多路复用器的输出将该输出时钟信号提供为同步的时钟信号，并且其中控制电路适于在n个延迟锁定环电路之间切换， 内部时钟信号的相位根据内部时钟信号和参考时钟信号之间的当前相移而相继移位。
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