-
公开(公告)号：US07688126B2
公开(公告)日：2010-03-30
申请号：US12362247
申请日：2009-01-29
申请人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
发明人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
IPC分类号： H03H11/26
摘要： A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
摘要翻译： 公开了一种延时电路，并且包括具有第一延迟电路和至少连接在下游的第二延迟电路的延迟线。 内插电路用于产生由延迟线中延迟的连续信号导出的中间信号。
-
公开(公告)号：US07564284B2
公开(公告)日：2009-07-21
申请号：US11728442
申请日：2007-03-26
申请人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
发明人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
IPC分类号： H03H11/26
摘要： A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
摘要翻译： 公开了一种延时电路，并且包括具有第一延迟电路和至少连接在下游的第二延迟电路的延迟线。 内插电路用于产生由延迟线中延迟的连续信号导出的中间信号。
-
公开(公告)号：US07900114B2
公开(公告)日：2011-03-01
申请号：US12395490
申请日：2009-02-27
IPC分类号： G01R31/28
CPC分类号： G01R31/3016
摘要： An electronic device includes an integrated circuit operating on the basis of an operating clock signal, an error detection circuit and a control circuit coupled to the error detection circuit. The control circuit is configured to increase the frequency of the operating clock signal starting from a nominal operating frequency of the integrated circuit, to evaluate a frequency increment at which an error is detected by the error detection circuit, and to reset the frequency of the operating clock signal to said nominal frequency.
摘要翻译： 电子设备包括基于操作时钟信号操作的集成电路，错误检测电路和耦合到该错误检测电路的控制电路。 控制电路被配置为增加从集成电路的标称工作频率开始的工作时钟信号的频率，以评估错误检测电路检测到错误的频率增量，并且重置操作频率 时钟信号到所述标称频率。
-
公开(公告)号：US20100223520A1
公开(公告)日：2010-09-02
申请号：US12395490
申请日：2009-02-27
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3016
摘要： An electronic device includes an integrated circuit operating on the basis of an operating clock signal, an error detection circuit and a control circuit coupled to the error detection circuit. The control circuit is configured to increase the frequency of the operating clock signal starting from a nominal operating frequency of the integrated circuit, to evaluate a frequency increment at which an error is detected by the error detection circuit, and to reset the frequency of the operating clock signal to said nominal frequency.
摘要翻译： 电子设备包括基于操作时钟信号操作的集成电路，错误检测电路和耦合到错误检测电路的控制电路。 控制电路被配置为增加从集成电路的标称工作频率开始的工作时钟信号的频率，以评估错误检测电路检测到错误的频率增量，并且重置操作频率 时钟信号到所述标称频率。
-
公开(公告)号：US20090128322A1
公开(公告)日：2009-05-21
申请号：US12362247
申请日：2009-01-29
申请人： Stephan Henzler , Siegmar Koppe , Dominik Lorenz
发明人： Stephan Henzler , Siegmar Koppe , Dominik Lorenz
摘要： A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
摘要翻译： 公开了一种延时电路，并且包括具有第一延迟电路和至少连接在下游的第二延迟电路的延迟线。 内插电路用于产生由延迟线中延迟的连续信号导出的中间信号。
-
公开(公告)号：US20080238652A1
公开(公告)日：2008-10-02
申请号：US11728442
申请日：2007-03-26
申请人： Stephan Henzler , Siegmar Koppe , Dominik Lorenz
发明人： Stephan Henzler , Siegmar Koppe , Dominik Lorenz
摘要： A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
摘要翻译： 公开了一种延时电路，并且包括具有第一延迟电路和至少连接在下游的第二延迟电路的延迟线。 内插电路用于产生由延迟线中延迟的连续信号导出的中间信号。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.02 秒)
