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公开(公告)号：US20130201048A1
公开(公告)日：2013-08-08
申请号：US13717410
申请日：2012-12-17
申请人： Junya MATSUNO , Tetsuro ITAKURA
发明人： Junya MATSUNO , Tetsuro ITAKURA
摘要： There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2̂n”; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.
摘要翻译： 提供了一种信号插值装置，包括：第一放大器，用于产生表示输入信号和第一参考电压之间的差的第一信号; 第二放大器，用于产生表示所述输入信号和第二参考电压之间的差的第二信号; 第一输出放大器，用于放大第一信号以产生第一输出信号; 第二输出放大器，用于放大第二信号以产生第二输出信号; 第三输出放大器，用于放大第一内插信号和第一信号的和以产生第三输出信号，第一内插信号表示通过将第一参考电压和第二参考电压之间的差除以“2n”而产生的电压， ; 以及第四输出放大器，用于放大第二信号和第一内插信号之间的差以产生第四输出信号。
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公开(公告)号：US20120105264A1
公开(公告)日：2012-05-03
申请号：US12981664
申请日：2010-12-30
申请人： Seung-Tak Ryu , Jong-In Kim , Ki-Jin Kim , Kwang Ho Ahn
发明人： Seung-Tak Ryu , Jong-In Kim , Ki-Jin Kim , Kwang Ho Ahn
IPC分类号： H03M1/38
摘要： An analog-to-digital converter includes: a first latch row corresponding to a first stage; a second latch row corresponding to a second stage; and a digital processor for encoding output signals of the second latch row and generating a digital signal. The first latch row includes a plurality of first latches that receive an analog input signal and reference voltages and operate in synchronization with a first clock signal, and the second latch row includes: a plurality of second latches that receive outputs signals of the plurality of first latches and operate in synchronization with a second clock signal delayed from the first reference clock; and a plurality of third latches that receive output signals of two neighboring latches of the plurality of first latches and operate in synchronization with the second clock signal by means of an interpolation technique.
摘要翻译： 模数转换器包括：对应于第一级的第一锁存行; 对应于第二级的第二锁存行; 以及用于对第二锁存行的输出信号进行编码并产生数字信号的数字处理器。 第一锁存行包括接收模拟输入信号和参考电压并与第一时钟信号同步操作的多个第一锁存器，并且第二锁存行包括：多个第二锁存器，其接收多个第一锁存器的输出信号 锁存并与从第一参考时钟延迟的第二时钟信号同步操作; 以及多个第三锁存器，其接收所述多个第一锁存器中的两个相邻锁存器的输出信号，并且通过插值技术与所述第二时钟信号同步地操作。
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公开(公告)号：US08049653B2
公开(公告)日：2011-11-01
申请号：US12717237
申请日：2010-03-04
申请人： Yuji Nakajima
发明人： Yuji Nakajima
IPC分类号： H03M1/34
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2200/378 , H03F2200/78 , H03F2203/45138 , H03M1/205
摘要： An amplifier that is operated between first and second power supplies includes a transistor pair having control terminals to which input signals are input, a load resistor pair that is provided between each transistor of the transistor pair and the first power supply, a constant current source that is provided between the second power supply and the transistor pair, and a first switch that is connected with the constant current source in series between the second power supply and the transistor pair, the first switch being turned on or off in accordance with a clock signal.
摘要翻译： 在第一和第二电源之间操作的放大器包括具有输入信号的控制端子的晶体管对，设置在晶体管对的每个晶体管和第一电源之间的负载电阻器对，恒流源， 设置在所述第二电源和所述晶体管对之间，以及第一开关，其与所述恒定电流源串联连接在所述第二电源和所述晶体管对之间，所述第一开关根据时钟信号导通或截止 。
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公开(公告)号：US20110001648A1
公开(公告)日：2011-01-06
申请号：US12439757
申请日：2007-09-04
申请人： Takeshi Ohkawa , Koichi Ono , Kouji Matsuura , Yukitosi Yamasita , Junji Toyomura , Shogo Nakamura , Norifimi Kanagawa
发明人： Takeshi Ohkawa , Koichi Ono , Kouji Matsuura , Yukitosi Yamasita , Junji Toyomura , Shogo Nakamura , Norifimi Kanagawa
CPC分类号： H03M1/0863 , H03M1/0682 , H03M1/141 , H03M1/205 , H03M1/365
摘要： A folding circuit and an analog-to-digital converter wherein a response to small signals is improved, a load on a clock signal can be reduced, and the increase of circuit area can be prevented. The circuit includes a reference voltage generating circuit that generates a plurality of differential voltages as reference voltages, and a plurality of amplification circuits that convert differential voltages between the plurality of reference voltages and an analog input voltage to differential currents, and output these differential currents. The output ends of the amplification circuits are alternately connected. Each of the amplification circuit is configured by a differential amplifier circuit having cascode output transistors (145, 146). A switch (144), which is turned on in synchronization with the control clock, is provided between the both sources of the cascode output transistors (145,146).
摘要翻译： 折叠电路和模数转换器，其中对小信号的响应得到改善，可以减少对时钟信号的负担，并且可以防止电路面积的增加。 该电路包括产生多个差分电压作为参考电压的参考电压产生电路和将多个参考电压之间的差分电压与模拟输入电压转换成差分电流的多个放大电路，并输出这些差分电流。 放大电路的输出端交替连接。 每个放大电路由具有共源共栅输出晶体管（145,146）的差分放大器电路构成。 在共源共栅输出晶体管（145,146）的两个源之间提供与控制时钟同步导通的开关（144）。
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公开(公告)号：US07688126B2
公开(公告)日：2010-03-30
申请号：US12362247
申请日：2009-01-29
申请人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
发明人： Stephan Henzler , Siegmar Köppe , Dominik Lorenz
IPC分类号： H03H11/26
摘要： A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
摘要翻译： 公开了一种延时电路，并且包括具有第一延迟电路和至少连接在下游的第二延迟电路的延迟线。 内插电路用于产生由延迟线中延迟的连续信号导出的中间信号。
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公开(公告)号：US06570522B1
公开(公告)日：2003-05-27
申请号：US10042190
申请日：2002-01-11
申请人： Tibi Galambos , Viktor Ariel , Jungwook Yang , Eliyahu Shamsaev
发明人： Tibi Galambos , Viktor Ariel , Jungwook Yang , Eliyahu Shamsaev
IPC分类号： H03M112
摘要： An analog-to-digital converter (ADC), including a plurality of first-level folded-differential-logic-encoders (FDLEs), coupled to receive an analog input signal and respective reference voltages and to provide respective outputs responsive to comparing a magnitude of the input signal to the respective reference voltages. The ADC has a second-level resultant FDLE, which is coupled to receive and combine the outputs of the first-level FDLEs to provide a digital value indicative of the magnitude of the input signal.
摘要翻译： 一种模数转换器（ADC），包括多个第一级折叠 - 差分逻辑编码器（FDLE），其被耦合以接收模拟输入信号和相应参考电压，并且响应于比较幅度 的输入信号。 ADC具有第二级结合FDLE，其被耦合以接收和组合第一级FDLE的输出，以提供指示输入信号的幅度的数字值。
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公开(公告)号：US20030043065A1
公开(公告)日：2003-03-06
申请号：US10027710
申请日：2001-12-20
发明人： Heng-Chih Lin , Baher S. Haroun
IPC分类号： H03M001/34
CPC分类号： H03M1/205 , H03M1/0682 , H03M1/365
摘要： A flash analog-to-digital converter having precise differential voltage interpolation without the use of silicide-blocked resistors. A reference conversion voltage output portion converts an analog input voltage on the basis of a plurality of reference voltages into a plurality of reference conversion voltages. An intermediate voltage generating portion includes a predetermined number of non-linear resistance units respectively provided between one voltage and the other voltage in pairs of a predetermined number of the plurality of reference conversion voltages to generate a plurality of intermediate voltages by resistance division using the predetermined number of non-linear resistance units. In addition, the intermediate voltage generating portion generates a plurality of conversion voltages. A digital data output portion outputs the digital output voltage on the basis of the plurality of conversion voltages using double interpolation. Each of the predetermined number of non-linear resistance units includes a first input terminal connected to the one voltage, a second input terminal connected to the other voltage, and a plurality of non-linear resistor elements having the same resistance value connected in series between the first and second input terminals. The plurality of intermediate voltages includes at least part of voltages obtained from one end of each of the plurality of non-linear resistor elements.
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公开(公告)号：US5867116A
公开(公告)日：1999-02-02
申请号：US682437
申请日：1996-07-17
摘要： In a multi-stage, multi-residue interpolating analog-to-digital converter (ADC), which is suitable for pipelined implementation, inputs of at least three amplifiers are "leapfrog" switched to adjacent nodes of a first interpolation ladder having discrete voltage levels established thereon. Pairs of the amplifiers drive second interpolation ladders to establish additional discrete voltage levels (in a nominal and an overlap conversion region) at nodes of the second interpolation ladders. A bank of comparators compares a predetermined threshold voltage, e.g., ground, to several of the discrete voltage levels at the nodes of the first interpolation ladder. The switches controlling which inputs of the amplifiers are connected to which nodes of the first interpolation ladder are controlled by a logic circuit which is driven by outputs of the bank of comparators. Alternatively, the bank of comparators compares an input voltage of the ADC to voltage levels established by the first interpolation ladder. In which case, the voltages at the nodes of the interpolation ladder to which the amplifiers are connected are amplified with respect to the input voltage of the ADC.
摘要翻译： 在适用于流水线实现的多级多残留内插模数转换器（ADC）中，至少三个放大器的输入“跨越”切换到具有离散电压电平的第一插值梯级的相邻节点 在其上建立。 对放大器驱动第二插值梯，以在第二插值梯的节点处建立额外的离散电压电平（在标称和重叠转换区域中）。 比较器组将预定阈值电压（例如接地）与第一内插梯的节点处的几个离散电压电平进行比较。 所述开关控制放大器的哪个输入端连接到第一插值梯形图的哪些节点由由比较器组的输出驱动的逻辑电路控制。 或者，比较器组将ADC的输入电压与由第一插值梯形图建立的电压电平进行比较。 在这种情况下，放大器所连接的内插梯的节点处的电压相对于ADC的输入电压被放大。
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公开(公告)号：US5640163A
公开(公告)日：1997-06-17
申请号：US498074
申请日：1995-07-05
申请人： Bram Nauta , Arnoldus G. W. Venes
发明人： Bram Nauta , Arnoldus G. W. Venes
摘要： A folding stage for a folding analog-to-digital converter includes a plurality of consecutive reference terminals providing ascending different reference voltages, a first summing node, a second summing node and a first output node. A plurality of differentially coupled transistor pairs wherein each of the pairs has a first transistor having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor having a main current path and a control electrode which is coupled to a respective one of the consecutive reference terminals. The main current path of the first transistor of the consecutive transistor pairs is coupled alternately to the first summing node and the second summing node, and the main current path of the associated second transistor is coupled alternately to the second summing node and the first summing node. A current-to-voltage converter includes a first resistor connected between the first output node and the first summing node to provide a first output voltage.
摘要翻译： 用于折叠模数转换器的折叠台包括提供不同参考电压的多个连续参考端子，第一求和节点，第二求和节点和第一输出节点。 多个差分耦合晶体管对，其中每对具有具有主电流路径的第一晶体管和耦合到用于接收要折叠的输入电压的输入端（IT）的控制电极和具有主电流路径的第二晶体管 电流路径和耦合到相应的一个连续参考端的控制电极。 连续晶体管对的第一晶体管的主电流路径被交替地耦合到第一求和节点和第二求和节点，并且相关联的第二晶体管的主电流路径被交替地耦合到第二求和节点和第一求和节点 。 电流 - 电压转换器包括连接在第一输出节点和第一求和节点之间以提供第一输出电压的第一电阻器。
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公开(公告)号：US5051746A
公开(公告)日：1991-09-24
申请号：US497285
申请日：1990-03-22
摘要： An interpolation circuit for an A/D converter comprises a first and a second pair of inputs (2, 2'; 3, 3') and at least three pairs of outputs (20, 20'; 24, 24'; 21, 21'). The pairs of inputs receive pairs of two input signals (V.sub.1, V.sub.1c, V.sub.5, V.sub.5c) which are substantially complementary to one another. At least two pairs of outputs (20, 20'; 24, 24') supply pairs of two substantially complementary output signals. A first output (21) of the third pair of outputs (21, 21') is coupled to a first input (2) of the first pair of inputs (2, 2'). The second output (21') of the third pair of outputs is connected to a circuit node other than one of the inputs of the first pair of inputs. This node may be, for example, the first input (3') of the second pair of inputs (FIG. 9). Another possibility is to make the node one end (38) of an impedance element (32) which has its other end coupled to the second input (2') of the first pair of inputs (FIG. 3).
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