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1.发明授权Enhancing interface characteristics between a channel semiconductor alloy and a gate dielectric by an oxidation process 有权通过氧化工艺增强沟道半导体合金和栅极电介质之间的界面特性公开(公告)号：US08247282B2
公开(公告)日：2012-08-21
申请号：US12905619
申请日：2010-10-15
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/331 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823857 , H01L21/28255 , H01L21/823807 , H01L21/823842 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66651
摘要： In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.
摘要翻译： 在复杂的晶体管元件中，可以通过减小在阈值调节半导体材料和栅极电介质材料之间形成的界面的粗糙度来减小包括阈值调节半导体合金的晶体管中的长期阈值电压偏移。 为此，阈值调节半导体材料的一部分可以被氧化，并且可以在形成高k电介质材料之前去除。
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2.发明授权Enhancing interface characteristics between a channel semiconductor alloy and a gate dielectric by an oxidation process 有权通过氧化工艺增强沟道半导体合金和栅极电介质之间的界面特性公开(公告)号：US08609482B2
公开(公告)日：2013-12-17
申请号：US13549184
申请日：2012-07-13
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823857 , H01L21/28255 , H01L21/823807 , H01L21/823842 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66651
摘要： In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.
摘要翻译： 在复杂的晶体管元件中，可以通过减小在阈值调节半导体材料和栅极电介质材料之间形成的界面的粗糙度来减小包括阈值调节半导体合金的晶体管中的长期阈值电压偏移。 为此，阈值调节半导体材料的一部分可以被氧化，并且可以在形成高k电介质材料之前去除。
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3.发明申请ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS 有权通过氧化过程提高通道半导体合金与栅极电介质之间的界面特性公开(公告)号：US20120282760A1
公开(公告)日：2012-11-08
申请号：US13549184
申请日：2012-07-13
IPC分类号： H01L21/20
CPC分类号： H01L21/823857 , H01L21/28255 , H01L21/823807 , H01L21/823842 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66651
摘要： In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.
摘要翻译： 在复杂的晶体管元件中，可以通过减小在阈值调节半导体材料和栅极电介质材料之间形成的界面的粗糙度来减小包括阈值调节半导体合金的晶体管中的长期阈值电压偏移。 为此，阈值调节半导体材料的一部分可以被氧化，并且可以在形成高k电介质材料之前去除。
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4.发明申请ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS 有权通过氧化过程提高通道半导体合金与栅极电介质之间的界面特性公开(公告)号：US20110129970A1
公开(公告)日：2011-06-02
申请号：US12905619
申请日：2010-10-15
IPC分类号： H01L21/336
CPC分类号： H01L21/823857 , H01L21/28255 , H01L21/823807 , H01L21/823842 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66651
摘要： In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.
摘要翻译： 在复杂的晶体管元件中，可以通过减小在阈值调节半导体材料和栅极电介质材料之间形成的界面的粗糙度来减小包括阈值调节半导体合金的晶体管中的长期阈值电压偏移。 为此，阈值调节半导体材料的一部分可以被氧化，并且可以在形成高k电介质材料之前去除。
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5.发明授权Enhancing deposition uniformity of a channel semiconductor alloy by an in situ etch process 有权通过原位蚀刻工艺提高沟道半导体合金的沉积均匀性公开(公告)号：US08324119B2
公开(公告)日：2012-12-04
申请号：US12775863
申请日：2010-05-07
IPC分类号： H01L21/31 , H01L21/42 , H01L21/324 , H01L21/477
CPC分类号： H01L29/78 , H01L21/823412 , H01L21/82345 , H01L21/823481 , H01L27/092
摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。
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6.发明授权Formation of a channel semiconductor alloy by depositing a hard mask for the selective epitaxial growth 有权通过沉积用于选择性外延生长的硬掩模来形成沟道半导体合金公开(公告)号：US08293596B2
公开(公告)日：2012-10-23
申请号：US12842439
申请日：2010-07-23
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842
摘要： A growth mask provided for the deposition of a threshold adjusting semiconductor alloy may be formed on the basis of a deposition process, thereby obtaining superior thickness uniformity. Consequently, P-channel transistors and N-channel transistors with an advanced high-k metal gate stack may be formed with superior uniformity.
摘要翻译： 可以基于沉积工艺形成用于沉积阈值调节半导体合金的生长掩模，从而获得优异的厚度均匀性。 因此，具有先进的高k金属栅极堆叠的P沟道晶体管和N沟道晶体管可以形成为具有优异的均匀性。
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7.发明申请FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY DEPOSITING A HARD MASK FOR THE SELECTIVE EPITAXIAL GROWTH 有权通过沉积选择性外延生长的硬掩模形成通道半导体合金公开(公告)号：US20110027952A1
公开(公告)日：2011-02-03
申请号：US12842439
申请日：2010-07-23
IPC分类号： H01L21/8238 , H01L21/8236 , H01L21/28
CPC分类号： H01L21/823807 , H01L21/823842
摘要： A growth mask provided for the deposition of a threshold adjusting semiconductor alloy may be formed on the basis of a deposition process, thereby obtaining superior thickness uniformity. Consequently, P-channel transistors and N-channel transistors with an advanced high-k metal gate stack may be formed with superior uniformity.
摘要翻译： 可以基于沉积工艺形成用于沉积阈值调节半导体合金的生长掩模，从而获得优异的厚度均匀性。 因此，具有先进的高k金属栅极堆叠的P沟道晶体管和N沟道晶体管可以形成为具有优异的均匀性。
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8.发明申请ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY AN IN SITU ETCH PROCESS 有权通过现场蚀刻过程增强通道半导体合金的沉积均匀性公开(公告)号：US20100289094A1
公开(公告)日：2010-11-18
申请号：US12775863
申请日：2010-05-07
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L29/78 , H01L21/823412 , H01L21/82345 , H01L21/823481 , H01L27/092
摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。
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