公开(公告)号：US20060193168A1

公开(公告)日：2006-08-31

申请号：US11331365

申请日：2006-01-13

申请人： Stephan Schroder ,  Herbert Benzinger ,  Georg Eggers ,  Manfred Proll ,  Jorg Kliewer

发明人： Stephan Schroder ,  Herbert Benzinger ,  Georg Eggers ,  Manfred Proll ,  Jorg Kliewer

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/404 ,  H01L27/10885

摘要： An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a complementary, second bit line and a voltage difference identified being amplified. The semiconductor memory according to the invention provides for that capacitor electrode which is not connected to the selection transistor to be connected to the complementary, second bit line. As a result, for an operating voltage with the same magnitude, larger quantities of charge can be stored in the storage capacitor since now the two mutually spread potentials output by the sense amplifier are used for biasing the storage capacitor. The resultant increase in the signal strength makes the semiconductor memory insensitive toward signal corruptions which arise for example in the case of operating voltages at different levels for selection transistors and for transistors in the signal amplifier.

摘要翻译： 集成半导体存储器件包括各自具有选择晶体管和存储电容器的存储单元。 这种类型的存储单元通常通过读出放大器中与存储器单元连接的位线的电位进行读取，其中互补的第二位线的电位和识别的电压差被放大。 根据本发明的半导体存储器提供了未连接到选择晶体管以连接到互补的第二位线的电容器电极。 结果，对于具有相同幅度的工作电压，由于现在由读出放大器输出的两个相互扩展的电位用于偏置存储电容器，所以可以将大量的电荷存储在存储电容器中。 信号强度的增加使得半导体存储器对信号损坏不敏感，例如在用于选择晶体管的不同电平的操作电压和信号放大器中的晶体管的情况下。

公开(公告)号：US20050195638A1

公开(公告)日：2005-09-08

申请号：US11071590

申请日：2005-03-04

申请人： Herbert Benzinger ,  Jorg Kliewer ,  Manfred Proll ,  Stephan Schroder

发明人： Herbert Benzinger ,  Jorg Kliewer ,  Manfred Proll ,  Stephan Schroder

IPC分类号： G11C7/12 ,  G11C11/00 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C7/02 ,  G11C7/12

摘要： An integrated semiconductor memory device includes a memory cell array (B1) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit (100) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET1) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A10) that applies a mid-voltage (VBLEQ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (VBLEQ) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.

摘要翻译： 集成半导体存储器件包括具有第一位线和第二位线（BL，/ BL）的存储单元阵列（B 1），可控电阻器（SW）和控制单元（100），其被配置为控制可控电阻器 。 在集成半导体存储器件的第一操作状态下，第一和第二位线经由第一可控开关（ET 1）彼此连接，并且还经由设置为低电阻的可控电阻（SW）连接， 涉及施加中间电压（V BAT）的连接（A 10），其中中压的电压电平为第一和第二电压电位之间的算术平均值 VBLH，VBLL）。 由于控制单元在集成半导体存储器件的第一操作状态下将可控电阻短暂地设置为非常低的电阻，所以第一和第二位线所需的时间段需要采用中间电压（V < SUB> BLEQ ）被缩短。 因此，将第一和第二位线的充电速度降低到中间电压的电容耦合影响的影响显着减小。

公开(公告)号：US20050248996A1

公开(公告)日：2005-11-10

申请号：US11123226

申请日：2005-05-06

申请人： Ralf Schneider ,  Stephan Schroder ,  Manfred Proll ,  Jorg Kliewer

发明人： Ralf Schneider ,  Stephan Schroder ,  Manfred Proll ,  Jorg Kliewer

IPC分类号： G05F1/595 ,  G11C5/14 ,  G11C7/00 ,  G11C11/4074

CPC分类号： G11C11/4074 ,  G11C5/145

摘要： An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

摘要翻译： 集成电路包括用于施加电源电压（Vext）的输入端（IN）和用于产生输出电压（Vout）的输出端子（A）。 包括第一可控电阻（T 1）和包括电荷泵（10）和第二可控电阻（T 2）的第二分支的第一分支连接在输入端（IN）和输出端（A）之间。 控制电路（20）以取决于输出电压的实际值（Vout）与期望值（VSout）的比值的方式改变第一和第二可控电阻（T 1，T 2）的电阻值 输出电压和电源电压的实际值（Vext）与电源电压的期望值（VSext）的比率。 结果，输出电压（Vout）可以实际上独立于电源电压的波动而稳定到期望值（VSout）。

公开(公告)号：US20050249002A1

公开(公告)日：2005-11-10

申请号：US11123221

申请日：2005-05-06

申请人： Jurgen Auge ,  Manfred Proll ,  Jorg Kliewer ,  Frank Schroeppel

发明人： Jurgen Auge ,  Manfred Proll ,  Jorg Kliewer ,  Frank Schroeppel

IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/48

CPC分类号： G11C29/48

摘要： An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.

摘要翻译： 集成半导体存储器包括具有存储有数据值的至少一个存储单元的存储单元阵列和具有计数器的评估电路。 在集成半导体存储器的测试期间，如果存储在存储单元中的数据值偏离期望值，则计数器的计数器读数被改变。 阈值由控制电路预先定义。 编程电路将输入侧的阈值与计数器的瞬时计数器读数进行比较。 如果计数器的计数器读数超过阈值，则编程元件从第一编程状态变为第二编程状态。 在测试结束之后，通过输出端读出编程元件的状态。 该方案可以推断集成半导体存储器的可能的故障原因。

公开(公告)号：US20050249016A1

公开(公告)日：2005-11-10

申请号：US11121175

申请日：2005-05-04

申请人： Koen van Zanden ,  Manfred Proll ,  Jorg Kliewer ,  Bjorn Wirker

发明人： Koen van Zanden ,  Manfred Proll ,  Jorg Kliewer ,  Bjorn Wirker

IPC分类号： G11C7/12 ,  G11C8/00 ,  G11C11/4091 ,  G11C29/00 ,  G11C29/50

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/12015 ,  G11C29/50012 ,  G11C2029/1204 ,  G11C2029/2602

摘要： An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.

摘要翻译： 集成半导体存储器可以在与控制时钟同步的正常操作状态下操作。 在测试操作状态下，集成半导体存储器与第一控制信号的控制时钟的时钟边沿同步地驱动，并独立于控制时钟启动测试运行。 利用第一控制信号驱动，可以由存储体地址选择的存储体中的选择晶体管截止。 之后，所选择的存储体中的位线被互连并以预定的预充电势驱动。 在预充电时间过去之后，通过应用的字线地址选择一个字线，并且连接到所选字线的所选存储体中的选择晶体管导通。 独立于控制时钟的时钟周期设置和测试预充电时间。

公开(公告)号：US07116737B2

公开(公告)日：2006-10-03

申请号：US10253793

申请日：2002-09-24

申请人： Georg Erhard Eggers ,  Jorg Kliewer ,  Ralf Schneider ,  Norbert Wirth

发明人： Georg Erhard Eggers ,  Jorg Kliewer ,  Ralf Schneider ,  Norbert Wirth

IPC分类号： H04L7/00

CPC分类号： G04F1/005 ,  G11C27/024 ,  H03K5/08 ,  H03K5/13 ,  H03K2005/00247

摘要： The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value. A device is also provided for counting the number of logic states of the comparison signal which occur after the acquisition instant, and for signaling that the predetermined time value has elapsed if the counted number of logic states is equal to a predetermined number of logic states which corresponds temporally to the predetermined time value.

摘要翻译： 本发明提供了一种信号通知预定时间值已经过去的装置，具有用于在时钟信号的时间分布中获取和存储时钟信号的振幅值的装置。 提供一种装置，用于连续地将获取和存储的时钟信号的振幅值与时钟信号的瞬时振幅值进行比较，并且用于输出具有第一逻辑状态的比较信号，如果时钟信号的瞬时振幅值小于 存储的振幅值，并且如果时钟信号的瞬时振幅值大于存储的振幅值，则具有第二逻辑状态。 还提供了一种装置，用于对在获取时刻之后发生的比较信号的逻辑状态数进行计数，并且用于发出指示如果计数的逻辑状态数等于预定数量的逻辑状态，则预定时间值已经过去 在时间上对应于预定时间值。

公开(公告)号：US20050001761A1

公开(公告)日：2005-01-06

申请号：US10816662

申请日：2004-04-02

申请人： Jorg Kliewer ,  Georg Weiss

发明人： Jorg Kliewer ,  Georg Weiss

IPC分类号： G01S7/35 ,  G01S7/40 ,  G01S13/34

CPC分类号： G01S13/343 ,  G01S7/352 ,  G01S7/4021 ,  G01S2007/356

摘要： A method for the linearization of frequency modulated continuous wave (FMCW) radar devices having non-linear, ramp-shaped, modulated transmitter frequency progression x(t). With this invention, a correction phase term for compensation of the phase error in the reception signal q(t) is calculated on the receiver side in this device.

摘要翻译： 一种用于线性化具有非线性，斜坡形调制发射机频率进展x（t）的调频连续波（FMCW）雷达装置的方法。 利用本发明，在该装置中的接收机侧计算用于补偿接收信号q（t）中的相位误差的校正相位项。

公开(公告)号：US20060053354A1

公开(公告)日：2006-03-09

申请号：US11214482

申请日：2005-08-29

申请人： Jorg Kliewer ,  Martin Versen

发明人： Jorg Kliewer ,  Martin Versen

IPC分类号： G11C29/00

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C29/025

摘要： The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit carrier. According to the method, a respective prescribed test signal is applied to each internal line of the component using a controllable test signal generator integrated in the component. Output signals applied to the connections of the circuit carrier are tapped off. Thereafter, the respective output signals tapped off are identified with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the wire configuration between the component connections and circuit carrier connections.

摘要翻译： 本发明涉及一种用于确定具有布置在其上的至少一个部件的电路载体的导线配置的测试方法，其中部件中的内部线以规定的顺序连接到部件连接，并且其中部件连接被连接到 电路载体。 根据该方法，使用集成在该部件中的可控测试信号发生器将各个规定的测试信号施加到部件的每条内部线路。 施加到电路载体的连接的输出信号被分接。 此后，使用用于确定部件连接和电路载体连接之间的导线配置的外部测试装置，利用施加到部件的内部线路的相应测试信号来识别各个输出信号。