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公开(公告)号：US5926480A
公开(公告)日：1999-07-20
申请号：US673118
申请日：1996-07-01
申请人： Stephen A. Deschaine , Clemente G. Garcia , Edward P. Traupman , Manouchehr Entezari , Mark J. Nietubyc , Werner L. Heissenhuber
发明人： Stephen A. Deschaine , Clemente G. Garcia , Edward P. Traupman , Manouchehr Entezari , Mark J. Nietubyc , Werner L. Heissenhuber
CPC分类号： H04Q11/04 , H04J3/0685 , H04J3/1635 , H04Q2213/13076 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13166 , H04Q2213/13213 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/1336 , H04Q2213/13381
摘要： An interface unit (12) for interfacing a digital loop carrier (16) to a digital cross-connect (14) comprises a control interface (22) coupled between the digital cross-connect (14) and digital loop carrier (16) for conversion and communication of control messages therebetween. A timing interface (32) is further coupled between the digital cross-connect (14) and digital loop carrier (16) for generally synchronizing the operations thereof. Further, a matrix interface (30) is coupled between the digital cross-connect (14) and digital loop carrier (16) for converting data rates and formats of data in the digital cross-connect (14) and digital loop carrier (16), so that network signals received by the digital loop carrier (16) are converted from a first format to a second format and communicated by the matrix interface (30) to the digital cross-connect (14) for cross-connection, and cross-connected data are converted from the second format to the first format and communicated to the digital loop carrier (16).
摘要翻译： 用于将数字环路载波（16）与数字交叉连接（14）接口的接口单元（12）包括耦合在数字交叉连接（14）和数字环路载波（16）之间用于转换的控制接口（22） 以及其间的控制消息的通信。 定时接口（32）还被耦合在数字交叉连接（14）和数字环路载体（16）之间，以使其操作大致同步。 此外，矩阵接口（30）耦合在数字交叉连接（14）和数字环路载体（16）之间，用于转换数字交叉连接（14）和数字环路载体（16）中的数据速率和数据格式， ，使得由数字环路载波（16）接收的网络信号从第一格式转换为第二格式，并由矩阵接口（30）传送到数字交叉连接（14）进行交叉连接， 连接的数据从第二格式转换为第一格式并传送到数字环路载体（16）。
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2.发明授权Apparatus and method for mapping E1 signals into a digital cross-connect matrix space 失效将E1信号映射到数字交叉连接矩阵空间中的装置和方法
公开(公告)号：US5883898A
公开(公告)日：1999-03-16
申请号：US673102
申请日：1996-07-01
CPC分类号： H04Q11/04 , H04J3/1635
摘要： Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of the first E1 signal are mapped into the space of a first DS1 signal in the logical space. The 8 DS0 signals of the first E1 signal are then mapped into the space of a second DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals may be mapped into the logical space of two DS1 signals in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.
摘要翻译： 提供了将E1信号映射到预定数量的DS1信号的逻辑空间中的装置和方法。 作为第一E1信号的一部分的24个选择的DS0信号被映射到逻辑空间中的第一DS1信号的空间中。 然后，第一E1信号的8个DS0信号被映射到逻辑空间中的第二DS1信号的空间中。 根据定义的逻辑空间，附加的E1信号可以以相同的方式映射到两个DS1信号的逻辑空间，直到在定义的逻辑空间中的预定数量的DS1信号空间被填充。
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3.发明授权Apparatus and method for mapping high density E1 signals into a digital cross-connect matrix space 失效将高密度E1信号映射成数字交叉连接矩阵空间的装置和方法
公开(公告)号：US5886994A
公开(公告)日：1999-03-23
申请号：US673012
申请日：1996-07-01
CPC分类号： H04Q11/04 , H04J3/1635 , H04Q2213/13076 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13166 , H04Q2213/13213 , H04Q2213/13292 , H04Q2213/13299
摘要： Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of each E1 signal are mapped into the space of one DS1 signal in the logical space. The remaining eight DS0 signals of every three E1 signal are then interleavingly mapped into the space of one DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals are mapped into the logical space in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.
摘要翻译： 提供了将E1信号映射到预定数量的DS1信号的逻辑空间中的装置和方法。 作为每个E1信号的一部分的24个选择的DS0信号被映射到逻辑空间中的一个DS1信号的空间中。 每三个E1信号的剩余八个DS0信号随后交错地映射到逻辑空间中一个DS1信号的空间。 根据定义的逻辑空间，附加的E1信号以相同的方式映射到逻辑空间中，直到定义的逻辑空间中的预定数量的DS1信号空间被填满。
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公开(公告)号：US5901024A
公开(公告)日：1999-05-04
申请号：US773267
申请日：1996-12-23
申请人： Stephen A. Deschaine , Mark J. Nietubyc , Werner L. Heissenhuber , Henry K. Lee , Mark W. Berry
发明人： Stephen A. Deschaine , Mark J. Nietubyc , Werner L. Heissenhuber , Henry K. Lee , Mark W. Berry
CPC分类号： H04M3/30 , H04M3/005 , H04M3/12 , Y10T307/469
摘要： Apparatus for redundancy circuit protection includes a controller (20), a plurality of circuits (22) coupled to the controller (20), and a redundancy switch (50) coupled between the plurality of circuits (22) and a network. The redundancy switch (50) is adapted for connecting or disconnecting selected ones of the plurality of circuits (22) to or from the network. In addition, a predetermined number of spare circuits (52) with similar functionality as the plurality of circuits (22) are coupled to the high density bank control unit (20), so that the redundancy switch (50) may connect or disconnect selected ones of the predetermined number of spare circuits (52) to the network and establish a transmission path from the controller (20) through the selected spare circuits (52) to the network.
摘要翻译： 用于冗余电路保护的设备包括控制器（20），耦合到控制器（20）的多个电路（22）和耦合在多个电路（22）和网络之间的冗余开关（50）。 冗余开关（50）适于将多个电路（22）中的选定电路（22）连接到或从网络断开。 此外，与多个电路（22）具有类似功能的预定数量的备用电路（52）耦合到高密度组控制单元（20），使得冗余开关（50）可以连接或断开所选择的 的预定数量的备用电路（52）发送到网络，并建立从控制器（20）通过所选择的备用电路（52）到网络的传输路径。
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公开(公告)号：US6128321A
公开(公告)日：2000-10-03
申请号：US994369
申请日：1997-12-19
CPC分类号： H04L41/00 , H04J3/085 , H04L12/24 , H04Q11/0478 , H04J2203/0003 , H04J2203/0041 , H04J2203/0042 , H04J2203/0058 , H04J2203/0089 , Y10S370/907
摘要： A centrally-managed switch for interconnecting a plurality of digital signals through a plurality of selectable switch ports and controlled by a central management unit includes a cross-connect having a plurality of plesiochronous primary rate signal ports for receiving a plurality of plesiochronous primary rate signals, each plesiochronous primary rate signal comprising a plurality of channels, the cross-connect operable to switch ones of the channels of an originating plesiochronous primary rate signal to a destination plesiochronous primary rate signal. The invention further comprises an add/drop multiplexer comprising a plurality of synchronous primary rate signal ports coupled to the second plurality of plesiochronous primary rate signal ports of the cross-connect and operable to receive a plurality of synchronous high-speed signals, each synchronous high-speed signal comprising a plurality of synchronous primary rate signals, the add/drop multiplexer operable to remove ones of the synchronous primary rate signals from an originating synchronous high-speed signal and to add synchronous primary rate signals to a destination high speed synchronous signal. The cross-connect and add/drop multiplexer receive commands from the central management unit, the central management unit operable to generate commands to configure the switch for switching of data between synchronous high speed signals at a channel level in the cross-connect, and to generate commands to configure the switch for insertion of data from an originating plesiochronous primary rate signal into a destination synchronous high-speed signal.
摘要翻译： 用于通过多个可选开关端口互连多个数字信号并由中央管理单元控制的集中管理的交换机包括具有多个准同步主速率信号端口的交叉连接，用于接收多个准同步主速率信号， 每个准同步主速率信号包括多个信道，所述交叉连接可操作以将始发准同步主速率信号的信道中的一个切换到目的地准同步主速率信号。 本发明还包括一个分插复用器，包括多个同步主速率信号端口，该多个同步主速率信号端口耦合到交叉连接的第二多个同步初级速率信号端口，并且可操作以接收多个同步高速信号，每个同步高 包括多个同步主速率信号的加速信号，所述分插复用器可操作以从始发同步高速信号中去除同步主速率信号中的一些，并将同步主速率信号添加到目的地高速同步信号。 交叉连接和分插复用器接收来自中央管理单元的命令，中央管理单元可操作以产生命令以配置用于在交叉连接中的信道级别的同步高速信号之间切换数据的开关，以及交叉连接 生成命令来配置交换机，用于将数据从始发的准同步主速率信号插入目的同步高速信号。
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