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1.发明授权Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories 失效在具有粗略目录的基于交换机的多处理系统中消除歧义指令的方法和装置
公开(公告)号：US6101420A
公开(公告)日：2000-08-08
申请号：US957543
申请日：1997-10-24
IPC分类号： G05B19/18
CPC分类号： G05B19/0421 , G05B2219/2213 , G05B2219/2227
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译： 用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。 在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。 存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。 每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。 受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。 通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。 耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。 消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。 因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。 使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。
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2.发明授权Low occupancy protocol for managing concurrent transactions with dependencies 失效用于管理具有依赖关系的并发事务的低占用协议
公开(公告)号：US6154816A
公开(公告)日：2000-11-28
申请号：US957565
申请日：1997-10-24
IPC分类号： G06F9/46 , G06F12/08 , G06F15/167 , G06F12/16
CPC分类号： G06F9/52 , G06F12/0813 , G06F12/0828
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译： 用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。 在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。 存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。 每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。 受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。 通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。 耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。 消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。 因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。 使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。
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3.发明授权Employing multiple channels for deadlock avoidance in a cache coherency protocol 失效在缓存一致性协议中使用多个通道来实现死锁避免
公开(公告)号：US6014690A
公开(公告)日：2000-01-11
申请号：US957531
申请日：1997-10-24
CPC分类号： G06F12/0828 , G06F12/0813 , G06F12/0817
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译： 用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。 在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。 存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。 每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。 受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。 通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。 耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。 消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。 因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。 使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。
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4.发明授权Shadow commands to optimize sequencing of requests in a switch-based multi-processor system 失效影子命令来优化基于交换机的多处理器系统中的请求排序公开(公告)号：US06279084B1
公开(公告)日：2001-08-21
申请号：US08957062
申请日：1997-10-24
IPC分类号： G06F1300
CPC分类号： G06F13/161 , G06F12/0826
摘要： The invention pertains to serializing local and remote references to a portion of a shared memory to optimize sequencing of requests in a switch-based, multi-processor system in which the local and remote references can occur concurrently. Usually, local accesses are typically much faster than remote accesses. Thus, in the interest of performance, both local and remote accesses are permitted to occur concurrently in the multiprocessing system. However, in one instance a local access can cause deadlock problems for a remote access. In addition, problems associated with coherency of the shared memory can also arise. Thus, in order to prevent deadlock problems and to maintain coherency of a shared memory, if a local reference to an address of memory has been forwarded to a switch, in this instance a hierarchical switch, then all subsequent references to that address of memory are forwarded to the hierarchical switch. The hierarchical switch has ordering properties that maintain the received order of inputs.
摘要翻译： 本发明涉及将本地和远程引用的序列化到共享存储器的一部分，以优化基于交换机的多处理器系统中的请求的排序，其中本地和远程引用可以同时发生。 通常，本地访问通常比远程访问快得多。 因此，为了表现，本地和远程访问允许在多处理系统中同时发生。 但是，在一个实例中，本地访问可能会导致远程访问的死锁问题。 此外，还可能出现与共享存储器的一致性相关的问题。 因此，为了防止死锁问题并保持共享存储器的一致性，如果对存储器的地址的本地引用已被转发到交换机，则在这种情况下是分层交换机，则所有后续对存储器地址的引用是 转发到分层交换机。 分层交换机具有维持接收的输入顺序的排序属性。
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5.发明授权Order supporting mechanisms for use in a switch-based multi-processor system 失效用于基于交换机的多处理器系统中的订单支持机制
公开(公告)号：US6122714A
公开(公告)日：2000-09-19
申请号：US957298
申请日：1997-10-24
IPC分类号： G06F12/08 , G06F9/46 , G06F15/167 , G06F12/16
CPC分类号： G06F9/52
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译： 用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。 在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。 存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。 每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。 受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。 通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。 耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。 消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。 因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。 使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。
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公开(公告)号：US20080243268A1
公开(公告)日：2008-10-02
申请号：US11695022
申请日：2007-03-31
CPC分类号： G05B15/02 , G06F9/3802
摘要： According to one example embodiment of the inventive subject matter, there is provided a mechanism that controls which prefetchers are applied to execute an application in a computing system by turning them on and off. In one embodiment, this may be accomplished for example with a software control process that may run in the background. In another example embodiment, this may be accomplished using a hardware control machine, or a combination of hardware and software. The prefetchers are turned on and off in order to increase the performance of the computing system.
摘要翻译： 根据本发明主题的一个示例性实施例，提供了一种机制，其控制哪些预取器被应用以通过打开和关闭计算系统来执行计算系统中的应用。 在一个实施例中，这可以例如通过可以在后台运行的软件控制过程来实现。 在另一个示例实施例中，这可以使用硬件控制机器或硬件和软件的组合来实现。 为了提高计算系统的性能，打开和关闭预取器。
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公开(公告)号：US20080235457A1
公开(公告)日：2008-09-25
申请号：US11726238
申请日：2007-03-21
申请人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely
发明人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0842
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在共享高速缓冲存储器的第一条目中的数据相关联以指示第一线程的优先级，并且将第二优先级指示符与存储的数据相关联的方法 在图形引擎的共享高速缓冲存储器的第二条目中指示第二线程的优先级。 描述和要求保护其他实施例。
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