公开(公告)号：US20120126847A1

公开(公告)日：2012-05-24

申请号：US12950584

申请日：2010-11-19

申请人： Stephen V. Kosonocky ,  Gregory K. Chen

发明人： Stephen V. Kosonocky ,  Gregory K. Chen

IPC分类号： G01R31/40

CPC分类号： G01R31/40

摘要： Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.

摘要翻译： 通过逐周期监测环形振荡器的性能来测量电源变化和抖动。 通过对在时钟周期内遍历的环形振荡器的级数进行计数来测量性能，并将遍历的级数映射到特定的电压电平。 计数器用于计数环形振荡器转数，锁存器用于在循环结束时锁存环形振荡器的状态。 基于计数器和锁存器，产生监视器输出，其还可以包括与初始化环形振荡器和计数器相关联的复位延迟的调整到已知状态。

公开(公告)号：US08593171B2

公开(公告)日：2013-11-26

申请号：US12950584

申请日：2010-11-19

申请人： Stephen V. Kosonocky ,  Gregory K. Chen

发明人： Stephen V. Kosonocky ,  Gregory K. Chen

IPC分类号： G01R31/40

CPC分类号： G01R31/40

摘要： Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.

摘要翻译： 通过逐周期监测环形振荡器的性能来测量电源变化和抖动。 通过对在时钟周期内遍历的环形振荡器的级数进行计数来测量性能，并将遍历的级数映射到特定的电压电平。 计数器用于计数环形振荡器转数，锁存器用于在循环结束时锁存环形振荡器的状态。 基于计数器和锁存器，产生监视器输出，其还可以包括与初始化环形振荡器和计数器相关联的复位延迟的调整到已知状态。

公开(公告)号：US10360496B2

公开(公告)日：2019-07-23

申请号：US15088543

申请日：2016-04-01

申请人： Gregory K. Chen ,  Jae-Sun Seo ,  Thomas C Chen ,  Raghavan Kumar

发明人： Gregory K. Chen ,  Jae-Sun Seo ,  Thomas C Chen ,  Raghavan Kumar

IPC分类号： G06N3/063 ,  G06N3/04

摘要： An apparatus and method are described for a neuromorphic processor design in which neuron timing information is duplicated on a neuromorphic core. For example, one embodiment of an apparatus comprises: a first neurosynaptic core comprising a plurality of neurons and a synapse array comprising a plurality of synapses to communicatively couple the plurality of neurons, each synapse connecting two neurons having a weight associated therewith, wherein a first neuron is to generate an output spike based on the weights of synapses over which inputs are received from the other neurons; a second neurosynaptic core also comprising a plurality of neurons and having at least one counter to maintain a count value indicative of spike timing for a second neuron, wherein a spike output of the second neuron in the second neurosynaptic core is communicatively coupled over a first synapse to the first neuron in the first neurosynaptic core; and a duplicate counter maintained within the first neurosynaptic core and synchronized with the counter from the second neurosynaptic core, the first neuron to use a first value from the duplicate counter to adjust the weight of the first synapse coupling the second neuron to the first neuron.

公开(公告)号：US10825509B2

公开(公告)日：2020-11-03

申请号：US16146932

申请日：2018-09-28

申请人： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

发明人： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C27/02 ,  G11C7/10 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418

摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

公开(公告)号：US20170185888A1

公开(公告)日：2017-06-29

申请号：US14757397

申请日：2015-12-23

申请人： Gregory K. Chen ,  Jae-Sun Seo

发明人： Gregory K. Chen ,  Jae-Sun Seo

IPC分类号： G06N3/063 ,  G06F9/445 ,  G06F13/42 ,  G06N3/04

CPC分类号： G06N3/04 ,  G06F13/4282 ,  G06N3/02 ,  G06N3/063

摘要： Systems and methods for an interconnection scheme for reconfigurable neuromorphic hardware are disclosed. A neuromorphic processor may include a plurality of corelets, each corelet may include a plurality of synapse arrays and a neuron array. Each synapse array may include a plurality of synapses and a synapse array router coupled to synapse outputs in a synapse array. Each synapse may include a synapse input, synapse output; and a synapse memory. A neuron array may include a plurality of neurons, each neuron may include a neuron input and a neuron output. Each synapse array router may include a first logic to route one or more of the synapse outputs to one or more of the neuron inputs.

公开(公告)号：US20150220470A1

公开(公告)日：2015-08-06

申请号：US14126910

申请日：2013-06-28

申请人： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Sudhir K. Satpathy ,  Ram K. Krishnamurthy

发明人： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Sudhir K. Satpathy ,  Ram K. Krishnamurthy

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4022 ,  G06F13/4282 ,  G06F15/7825 ,  H04L12/46 ,  H04L49/109 ,  H04L67/10 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，路由器包括多个输入端口和输出端口，其中路由器是源同步混合网络片上（NoC），以基于在路由器之间传送的控制流信号中的转换来实现NoC的路由器之间的通信。 描述和要求保护其他实施例。