公开(公告)号：US07795937B2

公开(公告)日：2010-09-14

申请号：US12402815

申请日：2009-03-12

申请人： Sterling Smith ,  Ellen Chen Yeh ,  Wen cai Lu

发明人： Sterling Smith ,  Ellen Chen Yeh ,  Wen cai Lu

IPC分类号： H03L7/06

CPC分类号： H04N5/126 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0996

摘要： A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.

摘要翻译： 具有自动调整锁定精度的校准机制的可扩展DLL（延迟锁定环路）电路。 延迟锁定环电路包括用于根据系统时钟产生多个相位信号的多相锁相环电路，其中相位信号之一是像素时钟; 相位检测器，用于根据像素时钟检测参考信号和反馈信号之间的积分相位误差和分数相位误差; 相位选择器，用于根据分数相位误差选择一个相位信号; 以及延迟电路，用于根据积分相位误差和所选择的相位信号偏移参考信号的相位，以产生输出信号。

公开(公告)号：US20090243679A1

公开(公告)日：2009-10-01

申请号：US12402815

申请日：2009-03-12

申请人： Sterling Smith ,  Ellen Chen Yeh ,  Wen cai Lu

发明人： Sterling Smith ,  Ellen Chen Yeh ,  Wen cai Lu

IPC分类号： H03L7/06 ,  H03L7/00 ,  H03H11/16

CPC分类号： H04N5/126 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0996

摘要： A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.

摘要翻译： 具有自动调整锁定精度的校准机制的可扩展DLL（延迟锁定环路）电路。 延迟锁定环电路包括用于根据系统时钟产生多个相位信号的多相锁相环电路，其中相位信号之一是像素时钟; 相位检测器，用于根据像素时钟检测参考信号和反馈信号之间的积分相位误差和分数相位误差; 相位选择器，用于根据分数相位误差选择一个相位信号; 以及延迟电路，用于根据积分相位误差和所选择的相位信号偏移参考信号的相位，以产生输出信号。