公开(公告)号：US07576562B1

公开(公告)日：2009-08-18

申请号：US11818845

申请日：2007-06-15

申请人： Sterling Whitaker ,  Lowell Miles ,  Jody Gambles ,  Gary K. Maki

发明人： Sterling Whitaker ,  Lowell Miles ,  Jody Gambles ,  Gary K. Maki

IPC分类号： H03K19/173

CPC分类号： H03K19/17768 ,  G01R31/31722

摘要： A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.

摘要翻译： 提供了可诊断的结构化逻辑阵列和相关联的过程。 提供了一种基本单元结构，其包括包括多个输入节点，多个选择节点和输出节点的逻辑单元，耦合到选择节点的多个开关，其中开关包括多个输入线，选择 线路和输出线路，耦合到输出节点的存储器单元，以及耦合到多个输入线路和多个开关中的选择线路的测试地址总线和程序控制总线。 多个输入节点中的每一个上的状态可被验证地从存储单元加载和读取。 提供可信内存块。 相关联的过程被提供用于测试和验证逻辑单元的多个真值表输入。

公开(公告)号：US20070109865A1

公开(公告)日：2007-05-17

申请号：US11527375

申请日：2006-09-25

申请人： Gary Maki ,  Jody Gambles ,  Sterling Whitaker

发明人： Gary Maki ,  Jody Gambles ,  Sterling Whitaker

IPC分类号： G11C11/34

CPC分类号： G11C11/4125 ,  H03K19/00338

摘要： A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q′. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

摘要翻译： 与传统逻辑器件相比，系统对单事件颠簸和/或单事件瞬态的灵敏度降低。 在特定实施例中，系统包括输入，逻辑块，偏置级，状态机和输出。 逻辑块耦合到输入端。 逻辑块用于实现逻辑功能，经由输入接收数据集，并通过将数据集应用于逻辑函数来生成结果f。 偏置级耦合到逻辑块。 偏置阶段用于从逻辑块接收结果并将其呈现给状态机。 状态机耦合到偏置级。 状态机用于通过偏置级接收由逻辑块产生的结果。 状态机配置为保留系统的状态值。 状态值通常基于由逻辑块生成的结果。 输出耦合到状态机。 输出用于提供状态机存储的值。 本发明的一些实施例产生双轨输出Q和Q'。 逻辑块通常包含组合逻辑，并且在尺寸和晶体管配置中与传统的CMOS组合逻辑设计类似。 然而，这些实施例的电路中只有很小一部分对单事件不正常和/或单事件瞬变敏感。