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公开(公告)号：US07795761B2
公开(公告)日：2010-09-14
申请号：US12317223
申请日：2008-12-19
申请人： Steven Huynh , Matthew A. Grant , Lin Chen
发明人： Steven Huynh , Matthew A. Grant , Lin Chen
IPC分类号： H01H9/54
CPC分类号： H02M3/158 , H02J7/0065 , H02M3/07 , Y10T307/50 , Y10T307/944
摘要： A power converter having a switched capacitor buck/boost operation has first and second switches coupled to a first switching node, third and fourth switches coupled to a second switching node, a capacitor coupled between the first and second switching nodes, and an inductor coupled to the first switching node. A switch controller controls the switches to operate in voltage step-down mode and voltage step-up mode depending on a difference between converter output voltage VOUT and converter input voltage VIN. In a buck-optimized topology operating in a step-down mode, an output current flowing through the first switching node flows through only one switch at a given time. In a boost-optimized topology operating in a step-up mode, an output current flowing through the first switching node flows through only one switch at a given time. As a result, a more compact and efficient power converter may be realized at lower cost.
摘要翻译： 具有开关电容降压/升压操作的功率转换器具有耦合到第一开关节点的第一和第二开关，耦合到第二开关节点的第三和第四开关，耦合在第一和第二开关节点之间的电容器以及耦合到 第一个交换节点。 开关控制器根据转换器输出电压VOUT和转换器输入电压VIN之间的差异控制开关工作在降压模式和升压模式。 在降压模式下工作的降压优化拓扑中，流过第一个开关节点的输出电流在给定的时间只流过一个开关。 在升压模式下工作的升压优化拓扑中，流过第一个开关节点的输出电流在给定时间只流过一个开关。 结果，可以以更低的成本实现更紧凑和高效的功率转换器。
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公开(公告)号：US20100156368A1
公开(公告)日：2010-06-24
申请号：US12317223
申请日：2008-12-19
申请人： Steven Huynh , Matthew A. Grant , Lin Chen
发明人： Steven Huynh , Matthew A. Grant , Lin Chen
IPC分类号： G05F1/46
CPC分类号： H02M3/158 , H02J7/0065 , H02M3/07 , Y10T307/50 , Y10T307/944
摘要： A power converter having a switched capacitor buck/boost operation has first and second switches coupled to a first switching node, third and fourth switches coupled to a second switching node, a capacitor coupled between the first and second switching nodes, and an inductor coupled to the first switching node. A switch controller controls the switches to operate in voltage step-down mode and voltage step-up mode depending on a difference between converter output voltage VOUT and converter input voltage VIN. In a buck-optimized topology operating in a step-down mode, an output current flowing through the first switching node flows through only one switch at a given time. In a boost-optimized topology operating in a step-up mode, an output current flowing through the first switching node flows through only one switch at a given time. As a result, a more compact and efficient power converter may be realized at lower cost.
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公开(公告)号：US20100199249A1
公开(公告)日：2010-08-05
申请号：US12322376
申请日：2009-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.
摘要翻译： 可编程模拟瓦片集成电路放置工具允许用户相对于所提出的多瓦功率管理集成电路（MTPMIC）中的第二PMIC瓦片的图形表示来操纵第一功率管理集成电路（PMIC）瓦片的图形表示 ）。 新颖的PMIC瓦片具有预定义的物理结构，包括总线部分和用于存储用于配置瓦片的配置信息的存储器结构。 当适当地放置在MTPMIC中时，所选择的瓦片的总线部分自动形成标准化总线，其适应功能性MTPMIC所需的所有信号通信。 在模拟电路设计中具有最少训练的远程用户可以命令在所提出的MTPMIC布局中放置各个瓦片。 当接收到指示对PMIC瓦片的放置的满意的用户响应时，该工具快速且自动地生成适于制造MTPMIC的物理布局数据。
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4.发明申请Communicating configuration information across a programmable analog tile to another tile 有权将可编程模拟图块中的配置信息传递到另一个图块公开(公告)号：US20100199247A1
公开(公告)日：2010-08-05
申请号：US12322375
申请日：2009-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F1/26 , G06F1/3203 , G06F12/1408 , G06F17/5063 , G06F2217/64 , G06F2217/78
摘要： A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
摘要翻译： 通过将第一集成电路瓦片中的瓦片配置信息通过第二集成电路瓦片传送到第三集成电路瓦片，在标准化总线上配置可编程模拟瓦片集成电路。 三个集成电路瓦片中的每一个是集成电路的一部分。 当瓦片彼此相邻放置时，形成标准化总线。 相邻瓦片的数据总线和控制信号导体排列并互连，使得每个信号导体电连接到每个瓦片。 可以使用数据总线和控制线将瓦片配置信息写入由任何所选择的瓦片中的地址识别的所选择的寄存器，而不管瓦片发送和瓦片接收信息的相对物理位置。 因此，瓦片配置信息可以通过任何数量的中间瓦片从一个瓦片传递到另一个瓦片。
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公开(公告)号：US08341582B2
公开(公告)日：2012-12-25
申请号：US12322373
申请日：2009-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5063 , G06F2217/78
摘要： A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.
摘要翻译： 可编程模拟瓦片集成电路配置工具在多瓦片电源管理集成电路（MTPMIC）中传达用于新型电力管理集成电路（PMIC）瓦片的功率管理控制特性查询请求控制要求信息。 配置工具通过网络收到用户对查询指示控制要求的响应。 PMIC瓦片包括配置寄存器。 存储在配置寄存器中的配置信息位值控制瓦片的功能电路的操作特性。 每个新型PMIC瓦片的配置寄存器可以在MTPMIC的标准化总线上的预定义地址处访问。 响应于用户响应，配置工具生成用于加载配置寄存器的适当的瓦片配置信息，使得MTPMIC内的PMIC瓦片被编程以满足用户的控制要求。
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公开(公告)号：US08225260B2
公开(公告)日：2012-07-17
申请号：US12322376
申请日：2009-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.
摘要翻译： 可编程模拟瓦片集成电路放置工具允许用户相对于所提出的多瓦功率管理集成电路（MTPMIC）中的第二PMIC瓦片的图形表示来操纵第一功率管理集成电路（PMIC）瓦片的图形表示 ）。 新颖的PMIC瓦片具有预定义的物理结构，包括总线部分和用于存储用于配置瓦片的配置信息的存储器结构。 当适当地放置在MTPMIC中时，所选择的瓦片的总线部分自动形成标准化总线，其适应功能性MTPMIC所需的所有信号通信。 在模拟电路设计中具有最少训练的远程用户可以命令在所提出的MTPMIC布局中放置各个瓦片。 当接收到指示对PMIC瓦片的放置的满意的用户响应时，该工具快速且自动地生成适于制造MTPMIC的物理布局数据。
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公开(公告)号：US20100199250A1
公开(公告)日：2010-08-05
申请号：US12322400
申请日：2009-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.
摘要翻译： 模拟平铺选择，放置，配置和编程（ATSPCP）工具通过网络传达电源管理特性查询。 该查询将显示给网页上的用户。 该查询是对电力管理集成电路（PMIC）的所需特性的征集。 在对查询的响应中接收到用户要求之后，该工具选择多个具有预定义物理结构的功率管理集成电路瓦片。 每个瓦片的预定义结构包括总线部分和用于存储瓦片的配置信息的存储器结构。 当组合在多平铺电源管理集成电路（MTPMIC）中时，所选择的电路板的总线部分自动形成标准化总线，以适应功能满足用户要求的MTPMIC所需的所有信号通信。 ATSPCP工具将每个选定的PMIC瓦片的物理布局数据组合，形成整个MTPMIC的复合物理布局数据。
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公开(公告)号：US08219956B2
公开(公告)日：2012-07-10
申请号：US12322400
申请日：2009-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.
摘要翻译： 模拟平铺选择，放置，配置和编程（ATSPCP）工具通过网络传达电源管理特性查询。 该查询将显示给网页上的用户。 该查询是对电力管理集成电路（PMIC）的所需特性的征集。 在对查询的响应中接收到用户要求之后，该工具选择多个具有预定义物理结构的功率管理集成电路瓦片。 每个瓦片的预定义结构包括总线部分和用于存储瓦片的配置信息的存储器结构。 当组合在多平铺电源管理集成电路（MTPMIC）中时，所选择的电路板的总线部分自动形成标准化总线，以适应功能满足用户要求的MTPMIC所需的所有信号通信。 ATSPCP工具将每个选定的PMIC瓦片的物理布局数据组合，形成整个MTPMIC的复合物理布局数据。
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公开(公告)号：US07869275B2
公开(公告)日：2011-01-11
申请号：US11888441
申请日：2007-07-31
申请人： Matthew A. Grant , David J. Kunst , Steven Huynh
发明人： Matthew A. Grant , David J. Kunst , Steven Huynh
IPC分类号： G11C11/34
摘要： An integrated circuit includes a plurality of tiles. One tile is a master tile. Other tiles contain writable registers of memory structures. Information for configuring circuitry of the tile is stored in the register in the tile. An individual one of the registers can be written via the master tile. Each memory structure of a register includes a non-volatile floating gate cell (that stores the configuration information) as well as a volatile cell. All transistors have the same gate insulator thickness. Although a programming pulse signal is applied to all memory structures, the state of the non-volatile cell of a memory structure is only changed if the state stored by the associated non-volatile cell differs from the state stored by the volatile cell. Floating gates are automatically refreshed by the programming pulse signal. By storing configuration information in each tile, inefficiencies associated with using blocks of non-volatile memory are avoided.
摘要翻译： 集成电路包括多个瓦片。 一块瓷砖是主砖。 其他瓦片包含可写寄存器的内存结构。 用于配置瓦片电路的信息存储在瓦片中的寄存器中。 可以通过主瓦片写入单个寄存器。 寄存器的每个存储器结构包括非易失性浮动栅极单元（存储配置信息）以及易失性单元。 所有晶体管具有相同的栅极绝缘体厚度。 虽然编程脉冲信号被应用于所有存储器结构，但是如果由相关联的非易失性单元存储的状态与由易失性单元存储的状态不同，则仅改变存储器结构的非易失性单元的状态。 浮动门由编程脉冲信号自动刷新。 通过将配置信息存储在每个瓦片中，避免了与使用非易失性存储器块相关联的低效率。
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公开(公告)号：US20080084743A1
公开(公告)日：2008-04-10
申请号：US11888441
申请日：2007-07-31
申请人： Matthew A. Grant , David J. Kunst , Steven Huynh
发明人： Matthew A. Grant , David J. Kunst , Steven Huynh
摘要： An integrated circuit includes a plurality of tiles. One tile is a master tile. Other tiles contain writable registers of memory structures. Information for configuring circuitry of the tile is stored in the register in the tile. An individual one of the registers can be written via the master tile. Each memory structure of a register includes a non-volatile floating gate cell (that stores the configuration information) as well as a volatile cell. All transistors have the same gate insulator thickness. Although a programming pulse signal is applied to all memory structures, the state of the non-volatile cell of a memory structure is only changed if the state stored by the associated non-volatile cell differs from the state stored by the volatile cell. Floating gates are automatically refreshed by the programming pulse signal. By storing configuration information in each tile, inefficiencies associated with using blocks of non-volatile memory are avoided.
摘要翻译： 集成电路包括多个瓦片。 一块瓷砖是主砖。 其他瓦片包含可写寄存器的内存结构。 用于配置瓦片电路的信息存储在瓦片中的寄存器中。 可以通过主瓦片写入单个寄存器。 寄存器的每个存储器结构包括非易失性浮动栅极单元（存储配置信息）以及易失性单元。 所有晶体管具有相同的栅极绝缘体厚度。 虽然编程脉冲信号被应用于所有存储器结构，但是如果由相关联的非易失性单元存储的状态与由易失性单元存储的状态不同，则仅改变存储器结构的非易失性单元的状态。 浮动门由编程脉冲信号自动刷新。 通过将配置信息存储在每个瓦片中，避免了与使用非易失性存储器块相关联的低效率。
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